AWGN信道下LDPC码的译码算法研究

在高斯白噪声(AWGN)信道情况下,针对LDPC码的译码算法进行深入分析后,对适用于低密度奇偶校验(LDPC)码的硬判决译码算法与软判决译码算法进行了仿真与对比分析,并通过引入乘性校正因子以降低软判决算法中对数域置信传播(LLR-BP)算法的变量消息相关性。仿真分析表明改进后的LLR-BP算法与原算法相比,在几乎不增加计算复杂度的情况下,其译码纠错性能得到了明显的改善。因而改进后的LLR-BP算法具有明显的优越性。     

LDPC编译码算法分析

低密度奇偶校验(LDPC)码是一种线性分组码,其纠错能力可以接近香农极限。针对LDPC码的编译码问题,分析了校验矩阵的构造方法。给出了LDPC码的编码算法以及算法的实现结构。分析了基于软判决的置信传播(BP)译码算法,并给出了可以进一步降低计算复杂度的简化译码方法。通过仿真对比了不同的译码算法在高斯信道下的译码性能。     

LDPC码在BPSK通信系统中的性能分析

LDPC编码在长码条件下具有接近Shannon极限的纠错能力,但是译码较为复杂,因此分析LDPC编码在短码条件下的编译码性能对于扩大LDPC编码的应用范围,降低译码设备的复杂度有着重要的意义。针对较短LDPC编码情况下的判决译码在BPSK系统中的应用,对基于BP算法的几种软判决译码算法进行了介绍,对算法在BPSK系统中的译码性能进行了仿真,仿真结果表明:基于对数测度的BP算法在LDPC短码条件下有着优良的译码性能,能够有效降低通信系统中编译码的复杂度。     

LDPC码在DSP上的实现

本文概述了LDPC码的编译码原理,重点论述在TI公司的DSP(TMS320C6416)上的(512,256)LDPC编译码器的算法实现,并给出其与(2,1,7)卷积码在AWGN信道条件下的纠错性能对比。对比表明(512,256)LDPC码比(2,1,7)软判决的卷积码在误码率为10-4时可具有1.5dB的编码增益。     

基于MRF的高性能二进制LDPC码译码算法

二进制LDPC码译码改进算法主要是提升硬判决性能或者降低软判决计算复杂度。本文应用高斯-马尔可夫随机场(Markov Random Field,MRF)模型实现信源参数估计,对信道译码端接收的比特序列进行对数似然比修正,在译码时加入信源的残留冗余信息来增加译码器的纠错能力。信源估计修正系数自适应可变,是由误码率参数调控。在计算复杂度不变的情况下,基于MRF的LDPC码译码算法有效提高了译码性能,降低误比特率     

基于联合判决消息传递机制的LDPC码译码算法研究

采用消息传递算法(Message passing algorithm)对LDPC码进行译码时,变量消息的振荡会引起错误的发生.本文以(600.300)非规则LDPC码仿真实验为例分析了不同译码效果下判决消息均值的分布特点,并结合环的特点,分析了译码产生错误判决的原因.研究了"纠删"型消息传递机制和联合判决迭代停止准则,针对判决消息出现振荡情况,提出以"纠删"方式处理变量消息的更新,并结合变量节点判决消息均值分布趋势与伴随式结果确定迭代终止条件.在此基础上,提出一种新的LDPC码译码算法.仿真分析表明,新的译码算法能够在减少迭代次数和降低译码复杂度的同时,有效提高译码的纠错性能.     

一种估测LDPC码最小距离的方法

由于LDPC码具有译码复杂度低,纠错性能好等众多优点,WiMAX 802.16e标准已将 LDPC 码作为OFDMA物理层的一种信道编码方案.本文采用从最小距离和码重分布的角度来研究LDPC码的纠错性能,深入研究了估计LDPC码距离特性的ANC算法,并利用此算法估测出几组LDPC码的最小距离.结果验证了ANC算法的正确...     

中长帧非规则LDPC码译码器的FPGA实现

LDPC(低密度奇偶校验码)是一种优秀的线性分组码,是目前距香农限最近的一类纠错编码。与Turbo码相比,LDPC码能得到更高的译码速度和更好的误码率性能,从而被认为是下一代通信系统和磁盘存储系统中备选的纠错编码。简要介绍了适于硬件实现的LDPC码译码算法,并基于软判决译码规则,使用Verilog硬件描述语言,在X ilinx V irtex2 6000 FPGA上实现了码率为1/2、帧长504bit的非规则LDPC码译码器。     

多天线系统的一种改进软判决译码算法

推导了采用垂直贝尔实验室分层空时(V-BLAST,Vertical-Bell Laborato-ries Layered Space-Time)结构的多天线(MIMO,Multiple Input and Multiple Out-put)系统中一种改进的软判决球译码(SD,Sphere-decoding)算法.结合LDPC码,仿真验证了该算法的性能与复杂度并与一种经典算法的性能及复杂度进行了比较.结果表明,合理选择参数,改进算法的计算复杂度可低于经典算法的计算复杂度,而其性能接近经典算法的性能.     

一种高性能低复杂度的LDPC译码器的FPGA实现

低密度校验码(LDPC码)所具有的优越性能和实用价值使其已经成为编码领域研究的热点。然而实际中LD-PC码的应用还有许多具有挑战性的问题,像如何降低译码的复杂度以及如何减少译码所需的大量硬件资源等。基于以上原因,研究一种高性能、低复杂度的软判决译码算法。这种译码算法较常用的硬判决译码算法性能出色,同时较一般的迭代译码算法的收敛速度快,并且可以部分并行译码,需要的存储量很小,能够大幅度降低LDPC译码的硬件实现复杂度,具有实际应用价值。     

Efficient GPU and CPU-based LDPC decoders for long codewords

The next generation DVB-T2, DVB-S2, and DVB-C2 standards for digital television broadcasting specify the use of low-density parity-check (LDPC) codes with codeword lengths of up to 64800 bits. The real-time decoding of these codes on general purpose computing hardware is useful for completely software defined receivers, as well as for testing and simulation purposes. Modern graphics processing units (GPUs) are capable of massively parallel computation, and can in some cases, given carefully designed algorithms, outperform general purpose CPUs (central processing units) by an order of magnitude or more. The main problem in decoding LDPC codes on GPU hardware is that LDPC decoding generates irregular memory accesses, which tend to carry heavy performance penalties (in terms of efficiency) on GPUs. Memory accesses can be efficiently parallelized by decoding several codewords in parallel, as well as by using appropriate data structures. In this article we present the algorithms and data structures used to make log-domain decoding of the long LDPC codes specified by the DVB-T2 standard??at the high data rates required for television broadcasting??possible on a modern GPU. Furthermore, we also describe a similar decoder implemented on a general purpose CPU, and show that high performance LDPC decoders are also possible on modern multi-core CPUs.     

DVB-S2中LDPC和积译码的GPU实现

第二代卫星数字广播系统DVB-S2采用接近Shannon限的LDPC码作为内码.在LDPC译码方式中,软判决的和积译码性能最佳,但是由于其采用大量浮点数运算,使得译码器的软硬件实现都较困难.为此,提出一种采用图形处理器(GPU)编程进行译码的实现方式.GPU的并行处理功能使其可以同时满足高精度浮点运算和高速实时解码的要求,为DVB-S2的实际应用提供了新的思路.采用计算机上NVIDIA GeForce 9600显卡编程环境,实现了满足高清视频要求的信息吞吐速率.     

一种准循环LDPC解码器的设计与实现

面向准循环LDPC码的硬件实现,定点分析了各种解码算法的解码性能,偏移量最小和(OMS)算法具备较高解码性能和实现复杂度低的特点.提出一种基于部分并行方式的准循环LDPC解码器结构,在FPGA上利用该结构成功实现了WiMAX标准中的LDPC解码器.FPGA验证结果表明,采用该结构的解码器性能优良,实现复杂度低,数据吞吐率高.     

FPGA implementation of low complexity LDPC iterative decoder

Low-density parity-check (LDPC) codes, proposed by Gallager, emerged as a class of codes which can yield very good performance on the additive white Gaussian noise channel as well as on the binary symmetric channel. LDPC codes have gained lots of importance due to their capacity achieving property and excellent performance in the noisy channel. Belief propagation (BP) algorithm and its approximations, most notably min-sum, are popular iterative decoding algorithms used for LDPC and turbo codes. The trade-off between the hardware complexity and the decoding throughput is a critical factor in the implementation of the practical decoder. This article presents introduction to LDPC codes and its various decoding algorithms followed by realisation of LDPC decoder by using simplified message passing algorithm and partially parallel decoder architecture. Simplified message passing algorithm has been proposed for trade-off between low decoding complexity and decoder performance. It greatly reduces the routing and check node complexity of the decoder. Partially parallel decoder architecture possesses high speed and reduced complexity. The improved design of the decoder possesses a maximum symbol throughput of 92.95 Mbps and a maximum of 18 decoding iterations. The article presents implementation of 9216 bits, rate-1/2, (3, 6) LDPC decoder on Xilinx XC3D3400A device from Spartan-3A DSP family.     

Memory Access Optimized Implementation of Cyclic and Quasi-Cyclic LDPC Codes on a GPGPU

Software based decoding of low-density parity-check (LDPC) codes frequently takes very long time, thus the general purpose graphics processing units (GPGPUs) that support massively parallel processing can be very useful for speeding up the simulation. In LDPC decoding, the parity-check matrix H needs to be accessed at every node updating process, and the size of the matrix is often larger than that of GPU on-chip memory especially when the code length is long or the weight is high. In this work, the parity-check matrix of cyclic or quasi-cyclic (QC) LDPC codes is greatly compressed by exploiting the periodic property of the matrix. Also, vacant elements are eliminated from the sparse message arrays to utilize the coalesced access of global memory supported by GPGPUs. Regular projective geometry (PG) and irregular QC LDPC codes are used for sum-product algorithm based decoding with the GTX-285 NVIDIA graphics processing unit (GPU), and considerable speed-up results are obtained.     

Two Bit-Flipping Decoding Algorithms for Low-Density Parity-Check Codes

In this letter, a low complexity decoding algorithm for binary linear block codes is applied to low-density paritycheck (LDPC) codes and improvements are described, namely an extension to soft-decision decoding and a loop detection mechanism. For soft decoding, only one real-valued addition per code symbol is needed, while the remaining operations are only binary as in the hard decision case. The decoding performance is considerably increased by the loop detection. Simulation results are used to compare the performance with other known decoding strategies for LDPC codes, with the result that the presented algorithms offer excellent performances at smaller complexity.     

对LDPC码的LLRBP算法研究

在LDPC译码时,使用IJLRBP算法其校验节点的计算复杂度十分高,而且当LDPC码中有许多的短环时,译码性能也会降低。基于以上的这些问题提出了一个新的混合校验变量过程,通过调整校验节点的处理振幅和变量节点的信息相关性来降低计算复杂度,其仿真过程表明在译码性能和运算复杂度上与LLRBP算法都有较大的提高。     

CORDIC instructions for LDPC decoding on SDR platforms

Wireless protocols strive to increase spectral efficiency and achieve high data throughput. Low-density parity-check (LDPC) codes are advanced forward error correction (FEC) codes that use iterative decoding techniques to achieve close to the Shannon capacity. Due to their superior performance, state-of-art wireless protocols, such as WiMAX and LTE Advanced, are adopting LDPC codes. LDPC codes come with the high cost of drastically increased computational effort for decoding. Among the proposed decoding algorithms, the belief propagation (BP) algorithm leads to a good approximation of an optimal decoder; however, it uses compute-intensive hyperbolic trigonometric functions. To reduce the computational complexity, typical LDPC decoder implementations use simplified algorithms, such as the min-sum algorithm, at the expense of reduced signal processing performance. Efficient and accurate methods to compute hyperbolic trigonometric functions can facilitate the use of the BP algorithm in real-time LDPC decoder implementations. This paper investigates hyperbolic COordinate Rotation DIgital Computer (CORDIC) instruction set architecture (ISA) extensions for software-defined radio (SDR) processors to compute the hyperbolic trigonometric functions for LDPC decoding efficiently. The CORDIC ISA extensions are evaluated on the low-power multi-threaded Sandbridge Sandblaster? SB3000 platform. The computational performance, numerical accuracy, hardware estimates, power consumption estimates, and memory requirements with the CORDIC ISA extensions are compared to a baseline implementation without these extensions on the SB3000.     

基于SISO的LDPC码盲译码算法研究

针对传统BP译码算法需要初始条件的缺点,本文提出了一种基于软输入软输出(SISO)的LDPC码盲译码算法,所提算法采用类似BP迭代译码算法步骤,通过对距离信息进行迭代处理,实现无需接收信号的信噪比和信道状态即可译码;同时,还将所提盲译码算法推广到多进制LDPC码的译码应用中。本文所提盲译码算法在初始状态难以确定以及接收信号信噪比难以估计的通信信道中具有重要价值。仿真结果表明,所提算法不论是在AWGN信道还是在瑞利衰落信道上都能取得优良的性能,不论是与标准BP译码算法还是与分层BP译码算法相比,在性能相近的情况下,计算复杂度都有所降低。