New Gate CD Control Technology Using CF 4 Plasma Treatment Following HBr/O 2 Plasma Treatment Step in Gate Etch Process Using Organic BARC

A new technology of resist trimming in a gate etch process using organic bottom antireflective coating (BARC) for accurate and stable gate critical dimension (CD) control of sub-0.18-mum node technology is presented in this paper. The new method uses an in situ CF₄ plasma treatment following an HBr/O₂ plasma treatment step as a part of the gate etch process to achieve a stable gate CD. The new method controls gate CD by trimming the photo resist masking gate line by reducing the effect of etch by-products, the source of CD variation, after etching organic BARC with HBr/O₂ plasma. It shows the markedly improved gate CD capability over the conventional one using just an HBr/O₂ plasma treatment for the CD control. We confirm that this new method is very useful and effective for the accurate gate CD control for sub-0.18-mum node metal-oxide semiconductor technology     

Effect of Topographical and Layout Factors on Gate CD Modeling for MOS Transistor Area

The gate critical dimension (CD) variation of ultra-large-scale integrated circuit (ULSI) devices should be reduced to improve the production yield. An examination of the formulation of a gate-CD model for the transistor area, including the static random access memory (SRAM), was conducted taking the topographical and layout effects into account. It was found that the formulation of a gate CD for transistor areas with a root-mean-square error (RMSE) of less than 1 nm was efficient. The coefficients of the shallow-trench-isolation (STI) step height and polycrystalline-silicon (poly-Si) thickness were found to be inversely proportional to the distance between the gate electrodes. It was found that this dependence is related to the reactive-ion-etching (RIE) lag in the etching process.      

Across Wafer Critical Dimension Uniformity Enhancement Through Lithography and Etch Process Sequence: Concept, Approach, Modeling, and Experiment

Across-wafer gate critical dimension (CD) uniformity impacts chip-to-chip performance variation vis-a-vis speed and power. Performance specification for across-wafer CD uniformity has become increasingly stringent as linewidth decreases to 90 nm and below. This paper presents a novel approach to improve across-wafer gate CD uniformity through the lithography and etch process sequence. The proposed approach is to compensate for upstream and downstream systematic CD variation components in the litho-etch process sequence by optimizing across-wafer post exposure bake (PEB) temperature profiles. More precisely, we first construct a temperature-to-offset model that relates the PEB temperature profiles to the setpoint offsets of multi-zone PEB plates. A second model relating across-wafer CD to setpoint offsets of PEB plates is then identified from CD scanning electron microscope measurements. Post-develop and post-etch CD uniformity enhancement methodologies are then proposed based on the CD-to-offset model and temperature-to-offset models. The temperature-to-offset model is determined to be more appropriate for use in CD uniformity control due to its superior fidelity and portability as compared with the CD-to-offset model. We demonstrate that about 1-nm reduction in standard deviation of post-etch CD variation was achieved in the verification experiment, which validated the efficacy of proposed CD uniformity control approach.     

氮注入多晶硅栅对超薄SiO_2栅介质性能的影响

p+ 多晶硅栅中的硼在 Si O2 栅介质中的扩散会引起栅介质可靠性退化 ,在多晶硅栅内注入 N+ 的工艺可抑制硼扩散 .制备出栅介质厚度为 4 .6 nm的 p+栅 MOS电容 ,通过 SIMS测试分析和 I- V、C- V特性及电应力下击穿特性的测试 ,观察了多晶硅栅中注 N+工艺对栅介质性能的影响 .实验结果表明 :在多晶硅栅中注入氮可以有效抑制硼扩散 ,降低了低场漏电和平带电压的漂移 ,改善了栅介质的击穿性能 ,但同时使多晶硅耗尽效应增强、方块电阻增大 ,需要折衷优化设计 .     

Gate capacitance attenuation in MOS devices with thin gatedielectrics

As gate oxides become thinner, in conjunction with scaling of MOS technologies, a discrepancy arises between the gate oxide capacitance and the total gate capacitance, due to the increasing importance of the carrier distributions in the silicon and polysilicon electrodes. For the first time, we quantitatively explore the combined impact of degenerate carrier statistics, quantum effects, and the semiconducting nature of the gate electrode on gate capacitance. Only by including all of these effects can we successfully model the capacitance-voltage behavior of sub-10 nm MOS capacitors. For typical devices, we find the gate capacitance to be 10% less than the oxide capacitance, but it can be attenuated by 25% or more for 4 nm oxides with polysilicon gates doped to less than 10²⁰ cm^-3     

Gate oxide damage reduction using a protective dielectric layer

Gate oxide damage from charge entering through the top surface of the gate electrode during plasma ashing, ion implantation, and LDD spacer oxide etching was measured using antenna structures. Significant charge damage to the 9.0 nm-thick gate oxide was detected for each of these processes. The damage was reduced by using a protective dielectric layer, in this case a thermally deposited TEOS oxide over the polycide gate electrode before gate definition. The dielectric appears to block charge penetration into the antenna. Damage can be reduced further by increasing the thickness of the dielectric layer; for a sufficiently thick layer (about 150 nm), charge entering through the top surface of the antenna was effectively eliminated     

优化了栅电极溅射工艺的难熔金属栅MOS电容的性能

论述了通过优化难熔金属栅电极的溅射工艺及采用适当的退火温度修复损伤来提高3nm栅氧W/TiN叠层栅MOS电容的性能.实验选取了合适的TiN厚度来减小应力,以较小的TiN溅射率避免溅射过程对栅介质的损伤,并采用了较高的N2/Ar比率在TiN溅射过程中进一步氮化了栅介质.实验得到了高质量的C-V曲线,并成功地把Nss(表面态密度)降低到了8×1010/cm2以下,达到了与多晶硅栅MOS电容相当的水平.     

Gate breakdown in MESFETs and HEMTs

A new model for gate breakdown in MESFETs and HEMTs is presented. The model is based upon a combination of thermally assisted tunneling and avalanche breakdown. When thermal effects are considered it is demonstrated that the model predicts increasing drain-source breakdown as the gate electrode is biased towards pinch-off, in agreement with experimental data. The model also predicts the gate current versus bias behavior observed in experimental data. The model is consistent with various reports of breakdown and light emission phenomena reported in the literature     

Advanced gate etching for accurate CD control for 130-nm node ASIC manufacturing

This paper presents a methodology for gate trim etching to obtain accurate critical dimension (CD) control for 130-nm node ASIC manufacturing. In order to reduce mask-to-mask CD variation in gate trim etching, correlation between mask layout and amount of gate trim is investigated. It is found that trim rate strongly depends on gate peripheral length. A novel feed-forward technology to reduce both wafer-to-wafer variation and mask-to-mask variation is developed with the knowledge of peripheral length effect. This technology can also reduce CD variation within die and the CD bias between dense and isolated lines is compensated by optical proximity correction rules. This novel feed-forward technology is one solution for improving every gate CD variation: within die, within wafer, wafer-to-wafer, and mask-to-mask.     

TFT AMLCD像素矩阵电路中栅延迟的模拟研究

建立了ａ－ＳｉＴＦＴＡＭＬＣＤ的等效电路模型,综合考虑栅信号线电阻、栅与源信号线的交叠电容以及ＴＦＴ导电沟道电容构成的ＲＣ（ＲｅｓｉｓｔｉｖｉｔｙＣａｐａｃｉｔａｎｃｅ）常数,模拟计算了栅信号延迟对液晶显示屏尺寸、显示分辨率及栅信号电极材料的依赖关系,为实现器件优化设计提供参考。     

Interdigitated Extended Gate Field Effect Transistor Without Reference Electrode

An interdigitated extended gate field effect transistor (IEGFET) has been proposed as a modified pH sensor structure of an extended gate field effect transistor (EGFET). The reference electrode and the extended gate in the conventional device have been replaced by a single interdigitated extended gate. A metal–semiconductor-metal interdigitated extended gate containing two multi-finger Ni electrodes based on zinc oxide (ZnO) thin film as a pH-sensitive membrane. ZnO thin film was grown on a p-type Si (100) substrate by the sol–gel technique. The fabricated extended gate is connected to a commercial metal-oxide–semiconductor field-effect transistor device in CD4007UB. The experimental data show that this structure has real time and linear pH voltage and current sensitivities in a concentration range between pH 4 and 11. The voltage and current sensitivities are found to be about 22.4 mV/pH and 45 μA/pH, respectively. Reference electrode elimination makes the IEGFET device simple to fabricate, easy to carry out the measurements, needing a small volume of solution to test and suitable for disposable biosensor applications. Furthermore, this uncomplicated structure could be extended to fabricate multiple ions microsensors and lab-on-chip devices.     

Gate oxide integrity on ITOX-SIMOX substrates and influence of testdevice geometry on characterization

The integrity of gate oxides on low-dose separation by implanted oxygen (SIMOX) substrates fabricated by the internal-thermal-oxidation (ITOX) process, so-called ITOX-SIMOX substrates, was evaluated, and the influence of test device geometry on the characterization was investigated. Characterization of time-dependent dielectric breakdown (TDDB) was performed for a gate oxide of 8.6-nm thick using lateral test devices. Experimental results show considerable influence of gate electrode geometry on the gate oxide integrity (GOI) characteristics. This can be explained by a model that includes a lateral parasitic resistance in the superficial Si layer beneath the gate electrode. Based on analysis using this model, a test device with a small gate array was proposed to reduce the influence of lateral parasitic resistance, and the advantage of the device was verified     

Electrical Properties of Ultra Thin Nitride/Oxynitride Stack Dielectrics pMOS Capacitor with Refractory Metal Gate

Electrical properties of high quality ultra thin nitride/oxynitride（N/O）stack dielectrics pMOS capacitor with refractory metal gate electrode are investigated，and ultra thin (＜2 nm＝ N/O stack gate dielectrics with significant low leakage current and high resistance to boron penetration are fabricated.Experiment results show that the stack gate dielectric of nitride/oxynitride combined with improved sputtered tungsten/titanium nitride (W/TiN) gate electrode is one of the candidates for deep sub-micron metal gate CMOS devices.     

Improvements in polysilicon etch bias and transistor gate control with module level APC methodologies

The targeting of transistor gate length is a primary driver of device performance. The targeting of the physical gate critical dimension (CD) greatly impacts the electrical gate dimension. Traditionally, continual monitoring and manual offsets to compensate for lithographic and etch equipment variability have been used to control gate CDs. This paper discusses how advanced process control techniques were applied to the 0.13-/spl mu/m polysilicon (poly) patterning process. Both scanner and etch equipment were controlled using a combination of feedforward and feedback loops. As a result, significant engineering labor was saved, and gate CD 3 sigma results improved 12%, correlating to improved device performance and enhanced yield.     

Advanced CD Control Technology for 65-nm Node Dual Damascene Process

This paper describes an advanced critical dimension (CD) control technology for a 65-nm node dual damascene process and beyond. A newly developed deposition enhanced shrink etching (DESE) process was introduced into both via and trench etching. This technology realizes not only dynamic via shrink ranging 40 nm but also accurate trench CD control by feedforward technology. Etching performance was investigated by electrical results of 65-nm Cu/low-k interconnects using porous chemical-vapor deposition SiOC. The 100% yields of 60-M via chains verified the DESE process robustness.     

Gate metallurgy effects in InAs/AlSb HFETs: Preliminary results and demonstration of surface fermi level shifts

The effect of gate metallurgy on depletion-mode InAs/AlSb heterostructure field-effect transistors (HFETs) is studied for the first time by carefully comparing the characteristics of Al- and Ti/Au-gate transistors. HFETs fabricated simultaneously from the same molecular beam epitaxial layers and processed identically, but differing only in the metal used for the gate electrode, feature very different gate and drain I-V characteristics. The metal dependence indicates that the Fermi level is not completely pinned at the surface of InAs/AlSb quantum wells. We also show that the gate metal modifies the charge control properties of InAs/AlSb HFETs: Al-gate HFETs exhibit an enhanced kink effect accompanied by a marked transconductance compression at zero gate bias, whereas the Ti/Au-gate devices exhibit nearly kink-free drain characteristics. The gate metal dependence is shown to be a consequence of the increased channel equilibrium electron concentration accompanying the Al-metallization.     

An Analytical Gate Tunneling Current Model for MOSFETs Having Ultrathin Gate Oxides

In this paper, we present a completely analytical model for the gate tunneling current, which can be used to get a first-order estimate of this parameter in present-generation MOSFETs, having ultrathin gate oxides and high substrate doping concentrations. The model has been developed from first principles, and it does not use any empirical fitting and/or correction parameters. It takes into account the quantization of the electron energy levels within the inversion layer of a MOSFET, which behaves similar to a potential well. Several interesting simplifications regarding this well structure have been made, and all these assumptions have been rigorously justified, both based on physical arguments as well as through numerical quantifications. An extremely interesting and important outcome of this procedure is a nonzero value of the wavefunction at the semiconductor-insulator interface, which is physically justified, however, contrary to what other existing literatures in this area assume. This procedure also led to a closed-form analytical expression for the inversion layer thickness. The interface wavefunction was used, in association with the tunneling probability through the gate oxide, and the carriers in transit model in the gate metal, to find the resultant gate tunneling current density as a function of the applied gate-to-body voltage. The results obtained from our simple and completely analytical model were compared with the experimental results reported in the literature, and the match is found to be excellent for varying oxide thicknesses and substrate doping concentrations, which justifies the authenticity of the model developed in this work here.     

高性能亚100nm栅长氮氧叠层栅介质难熔W/TiN金属栅电极CMOS器件

在国内首次将等效氧化层厚度为1.7nm的N/O叠层栅介质技术与W/TiN金属栅电极技术结合起来,用于栅长为亚100nm的金属栅CMOS器件的制备.为抑制短沟道效应并提高器件驱动能力,采用的关键技术主要包括:1.7nm N/O叠层栅介质,非CMP平坦化技术,T型难熔W/TiN金属叠层栅电极,新型重离子超陡倒掺杂沟道剖面技术以及双侧墙技术.成功地制备了具有良好的短沟道效应抑制能力和驱动能力的栅长为95nm的金属栅CMOS器件.在VDS=±1.5V,VGS=±1.8V下,nMOS和pMOS的饱和驱动电流分别为679和-327μA/μm.nMOS的亚阈值斜率,DIBL因子以及阈值电压分别为84.46mV/dec,34.76mV/V和0.26V.pMOS的亚阈值斜率,DIBL因子以及阈值电压分别为107.4mV/dec,54.46mV/V和0.27V.结果表明,这种结合技术可以完全消除B穿透现象和多晶硅耗尽效应,有效地降低栅隧穿漏电并提高器件可靠性.     

The Effect of an Yttrium Interlayer on a Ni Germanided Metal Gate Workfunction in SiO2/HfO2

In this letter, the tuning of a nickel fully germanided metal gate effective workfunction via a hyperthin yttrium (Y) interlayer at the bottom of the metal electrode was demonstrated on both SiO₂ and HfO₂. By varying the Y interlayer thickness from 0 to 9.6 nm, a full range of workfunction tuning from 5.11 to 3.65 eV has been achieved on NiGeY/SiO₂ stacks. It was also found that the chemical potential of the material that is adjacent to the gate electrode/gate insulator plays an important role in the determination of the effective workfunction. This work-function tuning window was observed to decrease to a range of 5.08-4.25 eV on NiGeY/HfO₂ stacks.     

超薄氮氧叠层栅介质的金属栅pMOS电容的电学特性

研究了高质量超薄氮化硅/氮氧化硅(N/O)叠层栅介质的金属栅pMOS电容的电学特性,制备了栅介质等效厚度小于2nm的N/O复合叠层栅介质,该栅介质具有很强的抗硼穿通能力和低的漏电流.实验表明这种N/O复合栅介质与优化溅射W/TiN金属栅相结合的技术具有良好的发展前景.