共查询到19条相似文献,搜索用时 531 毫秒
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基于二阶采样的免混频全数字化正交解调 总被引:8,自引:1,他引:7
提出了一种基于二阶采样技术的带通信号免混频全数字化正交解调方法。该方法直接对中频带通信号进行二阶采样,然后通过线性相数字滤波器获得正交的两路基带信号,该方法可省略正交混频环节,与基于一阶采样技术的免混频正交调方法相比,采样率的选择有更大的灵活性。 相似文献
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在实际的数字基带通信系统中,为使信息在基带信道中顺利传输,必须选择合适的基带信号,HDB3基带信号是常选信号之一.针对数字基带传输系统中HDB3信号的特点,采用基于FPGA的VHDL语言,在Quartus Ⅱ的环境中,实现HDB3数字基带信号的编码、译码器.本文主要分析NRZ(单极性不归零码)码与HDB3码(三阶高密度双极性码)之间的转换原理,并介绍用FPGA(现场可编程阵列)完成编译码器的设计思路. 相似文献
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数字正交解调器是软件无线电(SDR)接收机的重要部件,数字混频正交变换法是实现正交解调器的常用算法。本文针对软件无线电中传统数字混频正交变换法算法,根据理论推导,提出一种适用于多频段中频信号的改进结构的数字混频正交变换法。该改进算法将正交解调与低通滤波两个过程结合在一起实现,并且每输入M个输入采样值做一次输出滤波。通过分析和在可编程器件FPGA上的实验表明,该新结构完全实现了数字混频正交变换法,且能较大地减少所占用的FPGA上的RAM和乘法器资源,在相同的FPGA资源条件下,可以较大地提高中频数字正交解调器的邻道隔离性能,或者大幅度提高所允许的前端模数采样器(ADC)的采样频率。 相似文献
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An all-digital architecture is presented for implementing the front-end signal-processing functions in a quadrature modulator and demodulator for high bit-rate digital radio applications. A pair of CMOS chips has been designed and submitted for fabrication in a 1.25-μm process and is expected to accommodate symbol rates up to 35 MBd. The modulator chip accepts a pair of 8-b in-phase and quadrature data streams and generates a bandlimited IF output with an excess bandwidth factor of 35%. The demodulator chip accepts a digitized IF input signal and generates a pair of filtered in-phase and quadrature baseband signals. The modulator and demodulator chips each incorporate 40-tap multiplierless FIR (finite-impulse response) square-root Nyquist matched filters, and the cascade of the two chips achieves a peak intersymbol interference distortion of -54 dB. The modulator chip can generate any arbitrary signal constellation within a rectangular grid of 256×256 points. Thus, the all-digital implementation results in a generic chip set suitable for a wide variety of high bit-rate digital modem designs using formats such as M -ary PSK and QAM 相似文献
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The use of direct digital synthesis (DDS) to synthesize high-frequency analog signals has received much attention over the past decade. This technique allows modulation schemes such as FM and PM to be implemented with high fidelity using digital components. This paper investigates an improvement on the typical DDS approach of synthesizing the desired signal at an intermediate frequency. Instead, two quadrature baseband signals are generated, which are then mixed directly to the output center frequency. This method can be used to synthesize FM signals of arbitrarily high output frequency, using digital circuitry with considerably lower clock speeds 相似文献
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Saulnier G.J. Puckette C.M. IV Gaus R.C. Jr. Dunki-Jacobs R.J. Thiel T.E. 《Selected Areas in Communications, IEEE Journal on》1990,8(8):1500-1511
An all-digital demodulator/detector which is suitable for both analog FM and digital phase/frequency modulations is presented. The system uses complex sampling, which employs a single A/D (analog/digital) converter to sample the signal at an intermediate frequency (IF) and produce baseband in-phase (I ) and quadrature phase (Q ) signals, and a simplified technique for reducing the effect of the I /Q timing misalignment usually associated with this approach. The system also includes two detectors which operate simultaneously to provide noncoherent and differentially coherent detection, as well as automatic gain control (AGC) and automatic frequency control (AFC). The flexibility afforded by the two concurrent detectors in this all-digital system is shown to make it suitable for a wide range of applications. The theory behind the demodulator/detector system is described, and an implementation using a 1.25-μm bulk CMOS VLSI process is presented. Methods are shown for extending and improving the I /Q sampling misalignment correction technique, as well as for reducing the A/D sampling rate for a given IF frequency. Simulation and experimental results illustrate system performance for both analog and digital modulations 相似文献
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提出了一种二次载频测量方法,详细阐述了对高速跳频信号实时载频测量算法的工作原理。针对高速跳频信号特点,采用多路并行方法处理高速采样数据、快速傅里叶变换(Fast Fourier Transform,FFT)估计信号载频、数字正交下变频得到零中频信号。详细描述了基于可编程门阵列器件(Field-Programmable Gate Array,FPGA)的通过载频粗测、数字正交下变频、载频精测和载频合成的具体实现过程。以实际跳频信号为例,进行了仿真计算。结果表明设计稳定可靠、测量精度高。 相似文献