短帧Turbo码交织器的设计

本文给出一种分组交织器与最佳周期交织器相结合对数据进行交织的方案，可应用在短帧Turbo码交织器的设计中。通过对这种交织器的性能进行计算机模拟，本文得出在短帧Turbo码中该交织器的性能优于伪随机交织器和一般的分组交织器的性能。     

纠错编码系统交织器的设计

介绍了纠错编码系统中交织器的作用,以及交织器的几种类型的特性和实现方法,着重讨论了具有高度应变能力的伪随机交织器,最后对各种交织方法在不同干扰下的性能作了分析与对比,得出了一些基本结论。     

一种新型交织器的设计

在简单介绍两种常用交织器的基础上,给出了随机分组交织器的设计,并进行了计算机仿真。结果表明,此交织器设计简单,占用内存少,性能明显优于分组交织器,而仅次于随机交织器。     

可应用于VSAT通信系统中的差错控制方案

VSAT卫星通信系统是卫星通信领域中的一个重要应用。根据无线突发信道的特点，提出了一种交织器和前向纠错卷积码结合的差错控制方案。仿真结果表明，该方案可以提高抗误码性能，且使用m序列生成的伪随机交织器性能好于矩阵交织器。     

一种新的短帧交织器研究

对Turbo码中一种新的短帧交织器--幻方交织器进行了研究,根据距离特性目标函数对奇数阶幻方交织器的性能进行了详细分析.理论分析及仿真结果表明,在设计参数选择合理的情况下,奇数阶幻方交织器的性能优于传统矩阵交织器和随机交织器.     

Turbo码中快速交织器的设计

分析了交织器在Ｔｕｒｂｏ码中的重要作用，以及目前交织器存在的缺陷，介绍了一种快速交织器的设计方法。该交织器易于实现，具有交织时延低的突出优点。计算机仿真结果表明，该快速交织器可以获得优异的性能。     

分布式视频编码中符号Turbo码交织器的设计

分析了交织器在Turbo码中的作用,指出了现有的几种交织器的缺点.设计了两种新型的基于块交织的S随机交织器和基于伪随机交织的S随机交织器.仿真结果表明,与现有的几种交织器相比,这两种交织器在Turbo码译码迭代次数及延时方面性能更好,更适合于分布式视频编码系统.     

一种交织器和解交织器的FPGA电路实现

交织和解交织是组合信道纠错系统的一个重要环节,交织器和解交织器的实现方法有多种。本文利用Altera公司开发的Quartus软件平台和仿真环境,设计一种交织器和解交织器FPGA电路单倍实现的方法,并分析该电路实现的特点。 外交织的基本原理 实际信道中产生的错误往往是突发错误或突发错误与随机错误并存,如果首先把突发错误离散成随机错误,然后再去纠随机错误,那么系统的抗干扰性能就会进一步得到提高。交织器的作用就是将比较长的突发错误或多个突发错误离散成随机错误,即把错误离散化。交织器按交织方式可分为交织深度固定的交织器(如分组交织器和卷积交织器)和交织深度不断变化的随机交织器;按交织对象可分为码元交织器和码段交织     

Turbo码随机交织器的设计与实现

Turbo码中交织器性能的优劣将直接影响到Turbo码的译码性能.在分析交织器的设计准则和类型的基础上,利用m序列的遍历性,设计了一种基于m序列的随机交织器,并给出了基于FPGA的硬件实现方案.仿真结果表明,该随机交织器在实现输入数据随机分布方面性能优异,并降低了Turbo码的译码延迟.     

基于混沌交织的Turbo码及其性能仿真

基于非线性混沌映射提出了一种S随机混沌交织算法。在不同遮蔽程度的卫星移动衰落信道模型中,使用不同的解码算法,通过仿真比较了不同伪随机交织算法的Turbo码性能、不同的交织长度对系统性能的影响。仿真结果表明,在信噪比较低的卫星衰落信道中采用MAP、SOVA译码算法时,使用S随机混沌交织器的Turbo码性能均较使用伪随机交织器的Tur-bo码的性能有明显改进。     

Prunable Collision Free Random Interleaver Design

In this article we introduce a new collision free prunable random interleaver. The suggested interleaver is a joint structure involving rectangular and S-random interleaver. It comprises a general model for all kind of collision free prunable random interleavers. In addition, it can be designed for any number of parallel processors and any length of information sequence vector and can be considered also as a template for collision free prunable interleavers. The proposed interleaver can be used with all kind of turbo-like codes. The performance of the proposed interleaver is measured with parallel decodable serially concatenated convolutional codes (PDSCCCs) and compared to the PDSCCCs?? performance with collision full S-random interleaver.     

基于线性同余的IDMA交织器设计及分析

本文提出了一种新的基于线性同余的IDMA交织器设计方案, 并且给出了详细的交织器设计算法. 它能满足IDMA交织器设计中低存储量、容易产生交织序列、交织器同步数据少、交织器之间相关性小的要求. 本文的仿真结果证明了这种交织器性能优于伪随机交织器。     

2-Dimension Interleaver Design for IDMA Systems

A new design method interleavers, 2-dimension interleavers, are proposed for interleave division multiple access （IDMA） systems. With a same interleaving rule named I＇, the row indices and column indices of a traditional block interleaving matrix are scrambled to obtain an interleaver, which is marked as the master interleaver. F is produced by a loworder PN sequence generator. Two ways are provided for generating different interleavers. One is that all interleavers are generated by the circular shifting master interleaver. The other is that different inter leavers are generated by different Ts. Besides, we prove that the minimum distance between two adjacent bits resulted from 2-dimension interleaves is much larger than that of other schemes, such as random interleavers, power interleavers, and shiffting interleaves. The simulation results show that 2-dimension interleavers can achieve much better performance with much less resource consumption than random interleavers in IDMA systems.     

Turbo-TCM系统中几种交织器的性能研究

研究了Turbo码与网格编码调制(TCM)相结合的Turbo-TCM技术,将Turbo码中三类奇偶交织器的设计分别应用到Turbo-TCM中,并在Awgn信道和Rayleigh衰落信道下,对采用三种不同交织方式、不同帧长Turbo-TCM的性能进行了仿真。仿真结果表明,短帧条件下,Awgn信道中采用确定性奇偶交织器的Turbo-TCM性能最优,而Rayleigh衰落信道中三种交织方式的Turbo-TCM性能相近。长帧条件下,Awgn信道和Rayleigh衰落信道中,基于随机奇偶交织器的Tur-bo-TCM性能最优。     

Design of cyclic shift interleavers for Turbo Codes

In this paper we consider cyclic shift interleavers for turbo coding. The properties of cyclic shift interleavers are discussed and compared with S-random interleavers. It is shown that the cyclic shift interleavers are equivalent or better than the S-random interleavers in the ability to break low weight input patterns. We estimated the performance of turbo codes with cyclic shift interleavers and compared it with the performance of S-random interleavers for varions interleaver sizes. The simulation results show that a turbo code with a cyclic shift interleaver can achieve a better performance than an S-random interleaver if the parameters of the cyclic shift interleaver are chosen properly. In addition, the cyclic interleavers have the advantages of lower design complexity and memory requirements.     

Analysis and design of optimum interleaver for iterative receivers in IDMA scheme

In this paper, we propose a new tree based interleaver (TBI) to generate different chip‐level interleaving sequences for different users in an interleave division multiple access (IDMA) system, which reduces computational complexity. This method of generation also solves the memory cost problem and reduces the amount of information exchange between mobile stations (MSs) and base stations (BSs) required to specify the interleaver. Simulation results are presented to show that the proposed interleavers perform well as compared to random interleavers in an IDMA system. Copyright © 2008 John Wiley & Sons, Ltd.     

Design of interleavers for turbo codes: iterative interleavergrowth algorithms of polynomial complexity

This paper addresses the problem of designing interleavers for parallel concatenated convolutional codes (PCCCs) tailored to specific constituent codes. We start by establishing the role of the interleaver in the PCCC and the various parameters that influence the performance of the PCCC with a given interleaver. Subsequently, we define a canonical form of the interleaving engine denoted as the finite-state permuter (FSP) and demonstrate the minimal delay property of this canonical form. For any given permutation, we present a procedure for deriving the canonical FSP engine. We address the issue of implementation of the FSP and propose a very simple structure for the FSP. Next, using the structural property of the FSP engine, we develop a systematic iterative technique for construction of interleavers with a complexity that is polynomial in the interleaver size. Subsequently, we develop a cost function that, coupled with the iterative interleaver growth procedure, can be used to design optimized interleavers for PCCCs. We provide examples of application of the interleaver design technique, and compare the designed interleavers with some of the interleavers of comparable size found in the literature     

Turbo码交织器的等差错保护研究

Turbo码具有近Shannon限的突出纠错能力,是一种高性能的信道编码。文中分析了一般交织器的设计规则和进行Turbo码编码时存在的等差错保护问题。在此基础上,针对分组交织器提出了沿交织矩阵主对角线循环的信息写入机制,对于s 随机交织器增加了随机索引地址生成的约束条件,最终得到了两种具有等差错保护功能的Turbo码交织器。仿真结果表明,改进的交织器明显改善了Turbo码的误比特率性能。