A novel bulk-input low voltage and low power four quadrant analog multiplier in weak inversion

A new four quadrant voltage mode bulk input analog multiplier is presented .The proposed multiplier is designed to operate in weak inversion. Multiplication is done by driving the bulk terminals of the MOS devices which offers linear dynamic range of ±80 mV. The simulation shows, it has a linearity error of 5.6 %, THD of nearly 5 % and ?3 dB band width of 221 kHz. Total power consumption is very low i.e. 714 nW. The circuit operates at a supply voltage of 0.5 V and is designed using 180 nm CMOS technology. It is suitable for low power bioelectronics and neural applications.     

Characterization of surface states in HCl-grown oxides using MOS transient currents

A fast transient current (TC) technique has been developed for the characterization of majority carrier charge emission from surface states using MOS capacitors excited by a voltage step-function. This technique, with appropriate choice of initial and final biasing conditions, allows a rapid determination of the density of surface states (N_ss) and their capture cross section values (σ_n) in preselected regions of band gap using suitable temperature ambients. A low temperature (113°K) was used for regions close to the bottom of conduction band and room temperature and moderately low temperatures were used for the mid-gap region. Results of transient current measurements were compared with those obtained from thermally stimulated current and low frequency C-V measurements. The MOS devices were fabricated using [100] oriented n-type (6–8 Ω-cm) silicon on n⁺ substrates with HCl added to the oxidizing ambient. The detectability limit of the TC technique has been found to be approximately 1 × 10¹⁰ cm^?2 eV^?1 for the device area used.     

Wide-Linear-Range Subthreshold OTA for Low-Power, Low-Voltage, and Low-Frequency Applications

We propose a novel configuration of linearized subthreshold operational transconductance amplifier (OTA) for low-power, low-voltage, and low-frequency applications. By using multiple input floating-gate (MIFG) MOS devices and implementing a cubic-distortion-term-canceling technique, the linear range of the OTA is up to 1.1 Vpp under a 1.5-V supply for less than 1% of transconductance variation, according to testing results from a circuit designed in a double-poly, 0.8-$muhbox m$, CMOS process. The power consumption of the OTA remains below 1$muW$for biasing currents in the range between 1–200 nA. The offset voltage due to secondary effects (contributed by parasitic capacitances, errors and mismatches of parameters, charge entrapment, etc.) is of the order of a few ten millivolts, and can be canceled by adjusting biasing voltages of input MIFG MOS transistors.     

A CMOS MF energy harvesting and data demodulator receiver for wide area low duty cycle applications with 250 mV start-up voltage

A low voltage start-up energy harvesting medium frequency receiver is presented, for use as the power and synchronisation part of a remote sensor node in a wide area industrial or agricultural application. The use of embedded low bandwidth network synchronisation data permits very low operational duty cycle without the need for real time clocks or wake up receivers at each node with their associated continuous power drain. The receiver consists of a rectifier, a power management unit and a phase-shift keying demodulator. The rectifier is optimised for low start-up and operating voltage rather than power efficiency. With standard MOS thresholds the rectifier can cold start with only 250 mV peak antenna input, and useful battery charging is delivered with 330 mV peak input. The QPSK demodulator consumes 1.27 μW with a supply voltage of 630 mV at a data rate of 1.6 kbps with 1 MHz carrier frequency. The IC is implemented in a standard threshold 0.18 μm CMOS technology, occupies 0.54 mm² and can deliver 10.3 μW at 3 V to an external battery or capacitor.     

Novel high PSRR high-order temperature-compensated subthreshold MOS bandgap reference

Novel high power supply rejection ratio (PSRR) high-order temperature-compensated subthreshold metal-oxide-semiconductor (MOS) bandgap reference (BGR) is proposed in Semiconductor Manufacturing International Corporation (SMIC) 0.13 μm complementary MOS (CMOS) process. By adopting subthreshold MOS field-effect transistors (MOSFETs) and the piecewise-curvature temperature-compensated technique, the output reference voltage's temperature performance of the subthreshold MOS BGR is effectively improved. The subthreshold MOS BGR achieves high PSRR performance by adopting the technique of pre-regulator. Simulation results show that the temperature coefficient (TC) of the subthreshold MOS BGR is 1.38×10^?6/°C when temperature is changed from ?40 °C to 125 °C with a power supply voltage of 1.2 V. The subthreshold MOS BGR achieves the PSRR of ?104.54 dB, ?104.54 dB, ?104.5 dB, ?101.82 dB and ?79.92 dB at 10 Hz, 100 Hz, 1 kHz, 10 kHz and 100 kHz respectively.     

Design and performance analysis of low power LNA with variable gain current reuse technique

This paper presents a CMOS low power Variable Gain Low Noise Amplifier for 26–34 GHz in 45 nm process technology, which composes of cascaded complimentary common gate (CCG) stage and digital current steering amplifier. First stage is CCG stage, which helps in achieving the low power consumption and less area. Second stage is variable gain amplifier, uses current reuse technique as well as g_m-boost technique and has constant dc current to make the input impedance stable. Source degeneration technique cancel out MOS parasitic capacitance help in achieving linearity. Simulated maximum peak gain is 13.139 dB at 30.57 GHz and lowest peak gain is 7.75 dB at 26 GHz i.e. approximately flat over the entire band. Lowest NF is 3.08 dB at 32.6 GHz. Process corner simulation has been done for all four corners (S–S, S–F, F–S, F–F) showing robustness of LNA. Input return loss has value less than ? 9.58 dB while output return loss has less than ? 2.6 dB showing good matching; power consumption is 16 mW for dc current of 16 mA at 1 V. MOS active chip area is 76.727 µm².

     

Design, implementation and measurement of a 120 GHz 10 Gb/s phase-modulating transmitter in 65 nm LP CMOS

A novel mm-wave phase modulating transmit architecture, capable of achieving data rates as high as 10 Gb/s is presented at 120 GHz. The circuit operates at a frequency of 120 GHz. The modulator consists of a differential branchline coupler and a high speed 4-to-1 analog multiplexer with direct digital input. Both a QPSK as well as a 8QAM constellation are supported. To achieve high output power, a 9-stage power amplifier is designed and connected to the multiplexer output. The complete chip is integrated in a 65 nm low power CMOS technology. Capacitive neutralization is used to achieve high gain and good stability for the MOS devices. Also, various differential transmission line topologies are investigated to achieve high performance in terms of loss and area consumption.     

Evolution of MOS-bipolar power semiconductor technology

A review of the innovations that have led to the evolution of a power transistor technology based on MOS gate control is provided. This technology offers the advantage of very high input impedance, which allows the control of the devices using low-cost integrated circuits. The physics of operation of the two types of devices in this category, power MOSFETs and power MOS-bipolar devices, are described. Trends in process technology and device ratings are analyzed. Based on the superior performance of these devices, it is projected that they will completely displace the power bipolar transistor in the future     

Double MOS Loaded Circular Microstrip Antenna with Airgap for Mobile Communication

A novel model of a wide frequency range double MOS loaded circular microstrip patch antenna with airgap between ground plane and substrate is proposed. In this structure two metal oxide semiconductor (MOS) devices are loaded on the patch to enhance the operating frequency range of antenna. To investigate the antenna, different parameters such as resonance frequency, input impedance, frequency agility, VSWR, radiation pattern etc. are calculated and simulated. The resonant frequency of proposed 10 mm radius patch is upward shifted from 5.2 to 6.8 GHz using 1 mm airgap and by loading MOS, antenna can be tuned down to 1.27 GHz operating frequency, which leads to compactness and tunability of antenna. Proposed antenna can be tuned between 1.27 and 6.8 GHz frequency of operation which makes the antenna highly suitable for wide frequency range of mobile communication. The proposed double MOS loaded antenna possessed 82.94 % frequency agility. The antenna is worth for GPS, WLAN, UMTS, and WiMAX operations.     

Low-voltage low-power superior-order curvature-corrected voltage reference

A new superior-order curvature-corrected voltage reference will be presented. In order to improve the temperature behavior of the circuit, a double differential structure will be used, implementing the linear and the superior-order curvature corrections. An original ComplemenTary with Absolute Temperature voltage generator will be proposed, using exclusively MOS transistors biased in weak inversion for a low power operation of the voltage reference, having two great advantages: an important reducing of the circuit silicon area and an improved accuracy (matched resistors being replaced by matched MOS active devices). The superior-order curvature-correction will be implemented by taking the difference between two gate-source voltages of subthreshold-operated MOS transistors, biased at drain currents having different temperature dependencies: PTAT (ProporTional with Absolute Temperature) and square PTAT. In order to obtain a low-voltage operation of the circuit, the classical MOS transistor, which implements the elementary voltage reference, could be replaced by a Dynamic Threshold MOS transistor. The SPICE simulations confirm the theoretical estimated results, showing a temperature coefficient under 6 ppm/K for an extended input range 223 K < T < 333 K and for a supply voltage of 1.8 V and a current consumption of about 1 μA.     

Gate leakage current suppression and reliability improvement for ultra-low EOT Ge MOS devices by suitable HfAlO/HfON thickness and sintering temperature

Ultra-low effective oxide thickness (EOT) Ge MOS devices with different HfAlO/HfON stacks and sintering temperatures are investigated in this work. The suppression of gate leakage current and improvement of reliability properties can be achieved by either stacked gate dielectrics or a low sintering temperature. Especially, the qualities of the interface and high-k gate dielectric in Ge devices are significantly improved through a low sintering temperature. A 0.5 nm HfAlO/2.5 nm HfON gate stack and a sintering temperature at 350 °C are the suitable conditions to achieve low EOT, gate leakage, and good reliability for Ge MOS devices.     

Power delay optimization of nanoscale 4×1 multiplexer using CMOS based voltage doubler circuit

This paper represents a low leakage, highly efficient and delay improved 4×1 MUX with MOS based voltage doubler circuit cum augmented sleep transistors MOS configuration with nanoscale structure. The unique newly designed voltage doubler circuit is implemented as an additional circuit at the output of the implemented proposed design to step-up the voltage. It means that the output peak voltage is doubled due to the transient of both positive and negative cycles. This stepped-up voltage may be exploited as a stabilized supply for specific applications. The voltage doubler circuit is not enough to improve the overall performance of proposed 4×1 MUX design. In order to integrate the optimization criterion of leakage power and delay performance, the voltage doubler circuit is utilized along with the MOS configuration of augmented sleep transistors. To minimize the parameter of leakage power dissipation theMOSbased voltage doubler circuit cum augmented sleep transistorsMOSconfiguration is introduced. This will mitigate the redundant unused leakage power dissipation of the circuit. This additional circuitry brings out the aspired level of output voltage for the proposed and implemented 4×1 MUXwith better performance parameters. The whole simulation has been done for the 45nmtechnology. It is finally summarized that the leakage power dissipation is minimized up to 55% just around and the delay performance is also improved up to a desired level due to the utilization of MOS based voltage doubler circuit with the MOS configuration of augmented sleep transistors. In this paper, different combinations of MOS based augmented voltage doubler circuit implemented at the output of 4×1 MUX are represented.     

Bulk-driven class AB fully-balanced differential difference amplifier

This paper presents a new low-voltage class AB fully-balanced differential difference amplifier (FB-DDA) employing the bulk-driven technique. At the FB-DDA differential pairs the bulk terminal of the MOS transistors are used as signal inputs in order to increase the common-mode input range under low supply voltage. At the class AB output stages the bulk terminal of the MOS transistors are used as control inputs in order to adjust the quiescent currents and compensate them against the process and temperatures (P/T) variation. The voltage supply of the FB-DDA is 0.7 V and the quiescent power consumption is 8.3 µW. The open loop voltage gain is 68 dB and the gain–bandwidth product is 168 kHz for 10 pF capacitive load. The circuit performance was simulated in Cadence/Spectre environment using the TSMC 0.18 µm CMOS process.     

High-capacity, self-assembled metal-oxide-semiconductor decoupling capacitors

We combine nanometer-scale polymer self assembly with advanced semiconductor microfabrication to produce metal-oxide-semiconductor (MOS) capacitors with accumulation capacitance more than 400% higher than planar devices of the same lateral area. The self assembly technique achieves this degree of enhancement using only standard processing techniques, thereby obviating additional process complexity. These devices are suitable for use as on-chip power supply decoupling capacitors, particularly in high-performance silicon-on-insulator technology.     

A new design of a linear local-feedback MOS transconductor for low frequency applications

For medical devices, low frequency and low power applications are required, and a transconductor which has a low transconductance is needed. A conventional current division scheme for the low transconductance wastes operating current. This paper proposes an improved local-feedback MOS transconductor operating in subthreshold region. The proposed transconductor is optimally designed using maximally flat approximation method, Newton-Raphson method, and Downhill simplex method. From the optimization, two optimum values are obtained. Characteristics of the proposed transconductor are confirmed by simulation. Transfer characteristics of the proposed transconductor are linear, and the power consumption of the proposed transconductor is 1/60 as compared with the presented transconductor using current division scheme. The CMRR is around 70 dB, and the THD is lower than ?55 dB under a condition of that the frequency of the sinusoidal input is 100 Hz. As a demonstration of an application, the proposed transconductor is applied to a low frequency second order Butterworth filter. A cutoff frequency of the filter is 100 Hz. Simulation results show validities and availability of the proposed transconductor.     

FGMOS transistor based low voltage and low power fully programmable Gaussian function generator

In this paper floating gate MOS (FGMOS) transistor based fully programmable Gaussian function generator (GFG) is presented. The circuit combines the exponential characteristics of MOS transistor in weak inversion, tunable property of FGMOS transistor, and its square law characteristic in strong inversion region to implement the GFG. FGMOS based squarer is the core sub circuit of GFG that helps to implement full Gaussian function for positive as well as negative half of the input voltage. FGMOS implementation of the circuit provides low voltage operation, low power consumption, reduces the circuit complexity and increases the tunability of the circuit. The performance of circuit is verified at 0.75 V in TSMC 0.18 μm CMOS, BSIM3 and level 49 technology by using Cadence Spectre simulator. To ensure robustness of the proposed GFG, simulation results for various process corner variations have also been included.     

Nano Watt CMOS temperature sensor

In this paper, an ultra-low power embedded full CMOS temperature sensor based on sub-threshold MOS operation is designed in a 0.18 μm CMOS technology. It focuses on temperature measurement using the difference between the gate-source voltages of transistors operated in sub-threshold region that is proportional to absolute temperature. By using the proposed scheme the wide range supply voltage of 0.6–2.5 V with inaccuracy of +0.55 °C/V and total power consumption of merely 7 nW at 120 °C is achieved. The performance of the sensor is highly linear and the predicted temperature error is ±2 °C in the range of 10–120 °C. The sensor occupies a small area of 67 × 31 μm². Ultra-low power consumption of the sensor illustrates proper operation for low power applications such as battery powered portable devices, passive RFID tags and wireless sensor network applications.     

A low-voltage, low quiescent current, low drop-out regulator

The demand for low-voltage, low drop-out (LDO) regulators is increasing because of the growing demand for portable electronics, i.e., cellular phones, pagers, laptops, etc. LDO's are used coherently with dc-dc converters as well as standalone parts. In power supply systems, they are typically cascaded onto switching regulators to suppress noise and provide a low noise output. The need for low voltage is innate to portable low power devices and corroborated by lower breakdown voltages resulting from reductions in feature size. Low quiescent current in a battery-operated system is an intrinsic performance parameter because it partially determines battery life. This paper discusses some techniques that enable the practical realizations of low quiescent current LDO's at low voltages and in existing technologies. The proposed circuit exploits the frequency response dependence on load-current to minimize quiescent current flow. Moreover, the output current capabilities of MOS power transistors are enhanced and drop-out voltages are decreased for a given device size. Other applications, like dc-dc converters, can also reap the benefits of these enhanced MOS devices. An LDO prototype incorporating the aforementioned techniques was fabricated. The circuit was operable down to input voltages of 1 V with a zero-load quiescent current flow of 23 μA. Moreover, the regulator provided 18 and 50 mA of output current at input voltages of 1 and 1.2 V, respectively     

A FG-MOS Based Fully Differential Current Controlled Conveyor and Its Applications

This paper presents a new fully differential second generation current controlled conveyor (FDCCCII) based on differential pair topology, which employs floating gate MOS transistors (FG-MOS). It uses floating gate MOSFETs at the input stage and has rail-to-rail structure which performs with both positive and negative signals. This circuit has tunable parasitic resistance at its input port. It operates with low supply voltage (±0.8 V), low power consumption (lower than 3 mW at current bias of 1 mA), and wide range parasitic resistance (R _X ). This circuit has less MOSFET than the previous similar circuits and is suitable for integrated circuit design. To demonstrate the application of the proposed circuit, a fully differential current mode LC-ladder filter and a fully differential multifunction biquad filter are designed. Simulation results by HSPICE confirm validity of the proposed circuit and its application.     

Fundamental limitations in microelectronics—I. MOS technology

The physical phenomena which will ultimately limit MOS circuit miniaturization are considered. It is found that the minimum MOS transistor size is determined by gate oxide breakdown and drain-source punch-through. Other factors which limit device size are drain-substrate breakdown, drain ‘corner’ breakdown and substrate doping fluctuations. However these limitations are less severe than the oxide breakdown limitation mentioned above. Power dissipation and metal migration limit the frequency and/or packing density of fully dynamic and of complementary MOS circuits. In static non-complementary circuits, power dissipation is the principal limitation of the number of circuit functions per chip. The channel length of a minimum size MOS transistor is a factor of 10 smaller than that of the smallest present day devices. The tolerances required to manufacture such a transistor are compatible with electron beam masking techniques. It is thus possible to envision fully dynamic silicon chips with up to 10⁷–10⁸ MOS transistors per cm².