A dual current feedback op amp in CMOS technology

A CMOS circuit configuration implementing a current feedback or transimpedance op amp (CFB op amp) is presented. The architecture of the circuit is derived from similar bipolar CFB op amps. The properties of the CMOS implementation are similar to those of its bipolar counterparts, i.e., a high slew rate and a bandwidth which is independent of the closed-loop gain when the op amp is used with current feedback. Further, it is shown how two CFB op amps can be connected to achieve a non-slew-rate-limited voltage-mode op amp.     

一款高性能共源共栅运算放大器设计

基于CSMC 0.5μm标准CMOS工艺,采用复用型折叠式共源共栅结构,设计一种折叠式共源共栅运算放大器。该电路在5V电源电压下驱动5pF负载电容,采用Cadence公司的模拟仿真工具Spectre对电路进行仿真。结果表明,电路开环增益达到了71.7dB,单位增益带宽为52.79MHz,开环相位裕度为60.45°。     

Impedance boosting techniques based on BiCMOS technology

An impedance enhancement technique, based on a combination of bipolar and MOS devices, is presented. The technique uses negative active feedback action to boost the impedance level of a cascode circuit. This technique improves the gain of the conventional folded-cascode BiCMOS amplifier by the loop gain of the feedback loop. The BiCMOS-based impedance boosting circuit, compared to the CMOS version, offers the advantage of higher bandwidth together with higher output current capability. The SPICE simulations of a folded-cascode op amp based on this technique show that a 120 dB DC gain can be achieved. Application of the technique to a transducer resulted in a total harmonic distortion as low as 0.02% with 2 V_p-p input signals and an improvement of more than 10 dB in linearity, with respect to the case where no feedback was used     

Operational amplifier with 1-V rail-to-rail multipath-driven outputstage

A bipolar operational amplifier (op amp) with a rail-to-rail multipath-driven output stage that operates at supply voltages down to 1 V is presented. The bandwidth of this output stage is as high as possible, viz, equal to that of one of the output transistors, loaded by the output capacitance. The output voltage can reach both supply rails within 100 mV and the output current is ±15 mA. The op amp is designed to be loaded by a 100-pF capacitor and the unity-gain bandwidth is 3.4 MHz at a 60° phase margin. The voltage gain is 117 dB and the CMRR is 100 dB. The frequency behavior of the multipath-driven (MPD) topology has an improved performance when compared to that of previously presented low-voltage output stages. A figure of merit F_M for low-voltage op amps has been defined as the bandwidth-power ratio     

增益增强型CMOS运算放大器的自动优化算法

在增益增强型运算放大器优化中采用了自动设计方法,此方法在电路性能方程式和自适应遗传优化算法基础上对电路性能指标进行优化。该放大器在0.18μm CM O S工艺条件下中开环增益为92.1 dB,单位增益带宽积为1.78 GH z,相位裕度为55.1°和0.2%建立时间为1.27 ns,同时说明此优化设计方法的有效性。     

Low-power CMOS switched-capacitor lowpass filter using current conveyors

A new approach is proposed to the design of high-order switched-capacitor LPFs of megahertz cutoff frequency for communications channel selection. It essentially uses current conveyors instead of op amps to achieve low power consumption. A fifth-order Chebyshev LPF with a 1-MHz cutoff frequency is thus synthesized and fabricated in a 0.35-μm CMOS technology. The LPF consumes less than 10 mW from a 3-V power supply and exhibits a third harmonic distortion better than ?54 dB in response to a 1-V sinusoidal input at the cutoff frequency. The rms noise voltage is at most 1.9 mV in a 2-MHz bandwidth.     

An overview of feed-forward design techniques for high-gain wideband operational transconductance amplifiers

In this paper, feed-forward techniques are revised and used for the design of high-frequency operational transconductance amplifiers (OTA). For the same power consumption and similar transistor dimensions, the two- and three-path folded-cascode OTA's present both smaller settling error and faster response as compared to the typical folded-cascode topology.Also, a no-capacitor feed-forward (NCFF) compensation which uses a high-frequency pole-zero doublet to obtain high gain, high GBW and a good phase margin is discussed. The settling-time of the NCFF topology can be faster than that of OTA's with Miller compensation, even if the latter topology uses larger transconductance values. Experimental results for the multi-trajectory OTA's fabricated in the AMI 0.5 μm CMOS process demonstrate the feasibility of the feed-forward schemes.     

Simple technique for op amp continuous-time 1 V supply operation

A simple scheme for achieving continuous-time low-voltage operation of op amps is discussed. The scheme involves placing a floating battery in series with one of the op amp input terminals. Simulations and experimental results are presented that verify the proposed scheme with the example of a CMOS op amp that operates from a single 1 V supply and with 0.8 V signal swing     

A fourth-order bandpass delta-sigma modulator with reduced numbersof op amps

A switched-capacitor quadrature demodulation technique, which is insensitive to first-order errors resulting from 90° phase inaccuracy and path mismatch, is demonstrated to shift a band-pass spectrum directly to dc. A sampling rate of four times the passband center frequency facilitates the quadrature demodulation and removes the 90° phase error. Furthermore, the path-mismatch error is canceled using the same signal path repeatedly, thereby reducing the number of op amps. A fourth-order band-pass Δ-Σ modulator, integrated in an area of 1 mm² using 2-μm CMOS, consumes 0.8 mW with a single 3.3-V supply and exhibits an SNR of 56 dB within a 30-kHz bandwidth     

高性能折叠式共源共栅运算放大器的设计

折叠式共源共栅结构能够提供足够高的增益,并且能够增大带宽、提高共模抑制比和电源电压抑制比.基于Chartered 0.35 μm工艺,设计了一种折叠式共源共栅结构的差分输入运算放大器,给出了整个电路结构.Spectre仿真结果表明,该电路在3.3V电源电压下直流开环增益为121.5dB、单位增益带宽为12 MHz、相位裕度为61.4°、共模抑制比为130.1dB、电源电压抑制比为105 dB,达到了预期的设计目标.