Investigation on TG n-FinFET Parameters by Varying Channel Doping Concentration and Gate Length

In this paper, a 3D process of a nanometric n-channel fin field-effect transistor (FinFET) is discussed and the impact of variations of the fin parameter, the gate work function, and doping concentration on device characteristics are studied using the ATLAS Silvaco device simulator. Simulation results for various gate lengths are reported and analyzed. As the quantum effects are pronounced in nanoscale devices, we have included these effects in our study and simulation. We have then compared the achieved results to classical simulations to assess their performance limits. Finally, a comparison of our results with recently published data is presented to confirm our study.     

Maximum likelihood estimation of higher‐order integer‐valued autoregressive processes

Abstract. In this article, we extend the earlier work of Freeland and McCabe [Journal of time Series Analysis (2004) Vol. 25, pp. 701–722] and develop a general framework for maximum likelihood (ML) analysis of higher‐order integer‐valued autoregressive processes. Our exposition includes the case where the innovation sequence has a Poisson distribution and the thinning is binomial. A recursive representation of the transition probability of the model is proposed. Based on this transition probability, we derive expressions for the score function and the Fisher information matrix, which form the basis for ML estimation and inference. Similar to the results in Freeland and McCabe (2004) , we show that the score function and the Fisher information matrix can be neatly represented as conditional expectations. Using the INAR(2) specification with binomial thinning and Poisson innovations, we examine both the asymptotic efficiency and finite sample properties of the ML estimator in relation to the widely used conditional least squares (CLS) and Yule–Walker (YW) estimators. We conclude that, if the Poisson assumption can be justified, there are substantial gains to be had from using ML especially when the thinning parameters are large.     

3-D Simulation of Novel High Performance of Nano-Scale Dual Gate Fin-FET Inserting the High-K Dielectric TiO2 at 5 Nm Technology

Silicon - The evolution of integrated circuit is based on the miniaturization of dimension in the transistor Mosfet, this reduction causes the undesirable effect: short channel effects (SCE) and...     

Simple and fast convergent procedure to estimate recursive path analysis model

Behaviormetrika - BFGS procedure is classically used for the estimation of the parameters of a recursive Path Analysis model. In practice, BFGS does not present any problem of convergence. However,...     

Optimal parameters for performant heterojunction InGaP/GaAs solar cell

We demonstrated mainly some of the different parameters effects -as a function of temperature-as window layers, thickness, and doping of the various layers (emitter, base and BSF) on the performances of InGaP/GaAs solar cell. First, we have varied the molar fraction of different layers; their thickness and the doping of both emitters and bases. We have registered the result of each variation until obtaining optimal parameters. In a second stage, we have simulated the InGaP/GaAs cell without window layers which results in η = 12.47% and η = 22.14% for eliminating top and bottom windows respectively. Then, the elimination of layer BSFs(back surface field) on the back face of the considered cell causes a remarkable decrease in open circuit voltage Voc and output η which reached 1.57 V and 11.95% respectively. In a last stage, we optimized and simulated the performances of the InGaP/GaAs dual-junction solar cell for its optimal parameters while varying its operation temperature from 300 K to 375 K with an increment of 25 °C using a virtual wafer fabrication TCAD Silvaco. The optimization at 300 K led to the following results Icc = 15.19 mA/cm^?2, Voc = 2.53 V, FF = 91.32% and η = 25.43% which are close with those found in literature for In_(1?x)Ga_(x)P(x is molar fraction: x = 0.5). Therefore, we could determine the critical parameters of the cell and optimize its main parameters to obtain the highest performance for a dual junction solar cell. This work will pave the way with new prospects in the field of the photovoltaic. The structure simulation will simplify the manufacturing processes of solar cells; will thus reduce the costs while producing high outputs of photovoltaic conversion.     

Electrical Characteristics of 8-nm SOI n-FinFETs

This study is aimed at presenting the electrical characteristics of a nanoscale SOI n-channel fin field-effect transistor (FinFET) structure with 8 nm gate length using Al₂O₃ as the dielectric material and their sensitivity to the number of fins and fin-thickness with 3C-SiC material in the channel region. In this work, the numerical simulation tool Silvaco-Atlas is used to simulate the device in three-dimensions and to extract new results concerning the electrical characteristics of the device at room temperature (300 K) in comparison to earlier generations. The threshold voltage, subthreshold slope, transconductance, drain induced barrier lowering, leakage current, on-current, and On/Off current ratio are analyzed. Simulation results show that the higher drain current and transconductance are obtained by increasing the number of fins. The use of a higher value of gate dielectric constant can increase the drain current and improve the leakage current. It is found that reducing the fin-thickness is beneficial in reducing the subthreshold slope, drain induced barrier lowering, and leakage current. It should be highlighted that the achieved results can be useful for further manufacturing processes.     

Impedance boosting techniques based on BiCMOS technology

An impedance enhancement technique, based on a combination of bipolar and MOS devices, is presented. The technique uses negative active feedback action to boost the impedance level of a cascode circuit. This technique improves the gain of the conventional folded-cascode BiCMOS amplifier by the loop gain of the feedback loop. The BiCMOS-based impedance boosting circuit, compared to the CMOS version, offers the advantage of higher bandwidth together with higher output current capability. The SPICE simulations of a folded-cascode op amp based on this technique show that a 120 dB DC gain can be achieved. Application of the technique to a transducer resulted in a total harmonic distortion as low as 0.02% with 2 V_p-p input signals and an improvement of more than 10 dB in linearity, with respect to the case where no feedback was used     

Predicting required licensed spectrum for the future considering big data growth

This paper proposes a new spectrum forecasting (SF) model to estimate the spectrum demands for future mobile broadband (MBB) services. The model requires five main input metrics, that is, the current available spectrum, site number growth, mobile data traffic growth, average network utilization, and spectrum efficiency growth. Using the proposed SF model, the future MBB spectrum demand for Malaysia in 2020 is forecasted based on the input market data of four major mobile telecommunication operators represented by A–D, which account for approximately 95% of the local mobile market share. Statistical data to generate the five input metrics were obtained from prominent agencies, such as the Malaysian Communications and Multimedia Commission, OpenSignal, Analysys Mason, GSMA, and Huawei. Our forecasting results indicate that by 2020, Malaysia would require approximately 307 MHz of additional spectrum to fulfill the enormous increase in mobile broadband data demands.     

Development of High-Efficiency PERC Solar Cells Using Atlas Silvaco

Silicon - This paper presents the results of an investigation of Passivated Emitter Rear Cell (PERC) solar cell technology and the current understanding of the fundamental device physics. The...