Measurements and analysis of PLL jitter caused by digital switchingnoise

When integrating analog and digital circuits onto a mixed-mode chip, power supply noise coupling is a major limitation on the performance of the analog circuitry. Several techniques exist for reducing the noise coupling, of which one of the cheapest is separating the power supply distribution networks for the analog and digital circuits. Noise coupling from a digital noise-generating circuit through the power supply/substrate into an analog phase-locked loop (PLL) is analyzed for three different power supply schemes. The main mechanisms for noise coupling are identified by comparing different PLLs and varying their bandwidths. It is found that the main cause of jitter strongly depends on the power supply configuration of the PLL. Measurements were done on mixed-mode designs in a standard 0.25-μm digital CMOS process with a low-resistivity substrate. The same circuits were also implemented with triple-well processing for comparisons     

Fast multi-objective optimization of multi-parameter antenna structures based on improved MOEA/D with surrogate-assisted model

For multi-objective design of multi-parameter antenna structures, optimization efficiency and computational cost are two major concerns. In this paper, an improved multi-objective evolutionary algorithm based on decomposition (MOEA/D) is proposed to improve global optimization capability by diversity detection operation and mixed population update operation. Further, in order to reduce the computational cost, a hybrid optimization strategy integrating a dynamically updatable surrogate-assisted model into the improved MOEA/D is proposed. The numerical results of test functions show that our algorithm outperforms original MOEA/D, modified MOEA/D (M-MOEA/D), and nondominated sorting genetic algorithm II (NGSA-II) in terms of diversity. Experimental validation of Pareto-optimal planar miniaturized multiband antenna designs is also provided, showing excellent convergence and considerable computational savings compared to those previously published approaches.     

All-Digital PLL With Ultra Fast Settling

A fully digital frequency synthesizer for RF wireless applications has recently been proposed. At its foundation lies a digitally controlled oscillator with sufficiently fine frequency resolution to avoid analog tuning. The conventional phase/frequency detector, charge pump and RC loop filter are replaced by a time-to-digital converter and a simple digital loop filter. When implemented in highly scaled digital CMOS processes, the proposed architecture is more advantageous over conventional charge-pump-based phase-locked loops (PLLs) since it exploits signal processing capabilities of digital circuits and avoids relying on the fine voltage resolution of analog circuits. In this brief, we present novel techniques used in the all-digital PLL to achieve an ultra-fast frequency acquisition of <50 mus while maintaining excellent phase noise and spurious performance during transmission and reception. This approach has been validated and incorporated in commercial single-chip Bluetooth and Global System for Mobile Communications radios realized in deep-submicrometer CMOS     

A lifetime-aware analog circuit sizing tool

Reliability of CMOS circuits has become a major concern due to substantially worsening process variations and aging phenomena in deep sub-micron devices. As a result, conventional analog circuit sizing tools have become incapable of promising a certain yield whether it is immediately after production or after a certain period of time. Thereby, analog circuit sizing tools have been replaced by better ones, where reliability is included in the conventional optimization problem. Variation-aware analog circuit synthesis has been studied for many years, and numerous methodologies have been proposed in the literature. On the other hand, to our best knowledge, there has not been any tool that takes lifetime into account during the optimization. Besides, there are a number of different issues with lifetime-aware circuit optimization. For example, aging analysis is still quite problematic due to modeling and simulation deficiencies. Furthermore, a challenging trade-off between efficiency and accuracy is revealed during lifetime estimation in the optimization loop. Relatively expensive aging analysis is carried out for each candidate solution corresponding to a large number of simulations, so it is extremely important to deal with this trade-off. With regard to aforementioned these problems, this study proposes a novel lifetime-aware analog circuit sizing tool, which utilizes a novel deterministic aging simulator with adjustable step size. Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI) mechanisms are considered during the lifetime analysis, where the NBTI model was developed via accelerated aging experiments through silicon data. As case studies, two different OTA circuits are synthesized and results are provided to discuss the proposed tool.     

Interactive AC modeling and characterization of analog circuits via symbolic analysis

An advanced symbolic analyzer, called ASAP, has been developed for the automatic ac modeling of analog integrated circuits. ASAP works on a data base of model primitives and provides error-free symbolic expressions for the different system functions of analog circuits composed by the primitives. Both complete and simplified expressions can be calculated. Two simplification criteria have been implemented. The basic one is based on pruning the least significant terms in the different system function coefficients. This may yield important errors in pole and zero locations. To avoid that, an improved criterion has been developed where pole and zero displacements are forced to remain bounded. Also implemented are routines for symbolic pole/zero extraction and parametric ac circuit characterization. ASAP uses the signal flow graph method for symbolic analysis and has been written in the C language for portability. Together with portability, efficiency and ability to manage complexity have been fundamental goals in the implementation of ASAP. These features are demonstrated in this paper via practical examples.     

Switched-current delta-sigma A/D converters

Switched-current oversampling A/D converters are the ideal choice for mixed analog/digital design due to their complete compatibility with digital CMOS process and high tolerance to process variation. This paper presents a tutorial discussion on all the aspects of switched-current oversampling A/D converters, including structures, circuits, and practical issues. Three different modulator structures and six different types of switched-current circuits were used with an emphasis on low-voltage operation. Eight 3.3-V oversampling A/D converters were implemented and measured, and another one 1.2-V oversampling A/D converter was also implemented but yet to be measured.     

A precision variable-supply CMOS comparator

Several new techniques are presented for the design of precision CMOS voltage comparator circuits which operate over a wide range of supply voltages. Since most monolithic A/D converter systems contain an on-chip voltage reference, techniques have been developed to replicate the reference voltage in order to provide stable supply-independent DC bias voltages, and controlled internal voltage swings for the comparator. These techniques are necessary in order to eliminate harmful bootstrapping effects which can potentially occur in all AC coupled MOS analog circuits. An actively controlled biasing scheme has been developed to allow for differentially autozeroing the comparator for applications in differential A/D converter systems. A general approach for selecting the gain in AC-coupled gain stages is also presented. The comparator circuit has been implemented in a standard metal-gate CMOS process. The measured comparator resolution is less than 1 mV, and the allowable supply voltages range from 3.5 to 10 V.     

Exploiting bounds optimization for the semi-formal verification of analog circuits

This paper proposes a semi-formal methodology for modeling and verification of analog circuits behavioral properties using multivariate optimization techniques. Analog circuit differential models are automatically extracted and their qualitative behavior is computed for interval-valued parameters, inputs and initial conditions. The method has the advantage of guaranteeing the rough enclosure of any possible dynamical behavior of analog circuits. The circuit behavioral properties are then verified on the generated transient response bounds. Experimental results show that the resulting state variable envelopes can be effectively employed for a sound verification of analog circuit properties, in an acceptable run-time.     

System-level design for test of fully differential analog circuits

Several designs for test techniques for fully differential circuits have recently been proposed. These techniques are based on the inherent data encoding, the fully differential analog code (FDAC), present in differential circuits. These techniques have not previously been verified experimentally. In this paper, we report results from a fabricated test chip which incorporates design for test structures. The test chip is a fully differential fifth-order filter, and was fabricated on a 2-μm CMOS process. The test techniques implemented are derived from a system-level technique developed earlier. The test chip contains fault injection circuitry to emulate faults. Our results demonstrate that the FDAC is a viable design for test technique for analog circuits     

Frequency Response Verification of Analog Circuits Using Global Optimization Techniques

This paper develops a new formal technique to verify the frequency response of analog circuits using global optimization techniques. Since simulation-based approaches are unable to cover the design space, there is a need for formal approaches to verify large circuits. Drawing parallels from the digital domain, the verification problem in the analog domain is modeled as a non-linear optimization problem and solved using global optimization techniques by ensuring that the implementation response is bounded within an envelope around the specification. We also address the problem of verifying frequency response under the influence of parameter variations. Direct as well as indirect techniques are illustrated using accurate frequency response models. Experimental results are presented to show the effectiveness of the proposed methodology.     

基于可分解的多目标进化算法的PDN阻抗的优化

频率的电源分配网络设计是一个多目标优化问题。应用多目标进化算法优化电源分配网络的阻抗,其中去耦电容的个数和种类成为了PDN中两个需要优化的目标函数,这使得PDN中的输入阻抗,在截止频率内小于目标阻抗以达到设计要求。为解决这个问题,应用可分解的多目标进化算法,同时优化这两个目标,以获得期望的Pareto Front(PF)。实验证明,该设计方法易于实现,且效果良好、稳定性强。优化的PDN的输入阻抗满足设计要求并且优化的去耦电容的个数和种类逼近PF。     

基于重新匹配策略的ε约束多目标分解优化算法

针对MOEA/D算法中权重向量与个体分配不合理,导致种群多样性降低的问题,提出基于重新匹配策略的ε约束多目标分解优化算法.首先,对Tchebycheff分解策略进行理论分析,推导出关于多样性和收敛性的定理,从而为研究MOEA/D算法奠定理论基础.其次,为有效解决由于随机为权重向量分配个体造成种群多样性降低的问题,提出权重向量和个体间的重新匹配策略,合理地为权重向量分配个体,改善种群多样性.最后,提出的个体比较准则较好地兼顾多样性和收敛性,提高了算法的约束多目标优化性能.通过与5种优秀算法的对比实验结果表明,该文算法所求得的近似Pareto最优解集的分布性和收敛性均得到一定提高,相比于对比算法具有一定的优势.     

Simulation techniques for mixed analog/digital circuits

The techniques used in the iSPLICE3 simulator for the analysis of mixed analog/digital circuits are described. iSPLICE3 combines circuit, switch-level timing, and logic simulation modes and uses event driven selective-trace techniques. It also uses a hierarchical schematic capture package called iSPI (Simulation Program Interface) for design entry, circuit partitioning, and simulation control. The contributions here include a new DC solution method, a mixed-mode interface modeling technique, and an automatic partitioning approach for MOS logic circuits. The details of these three methods are provided, along with the architecture and transient simulation algorithms used in iSPLICE3. The results of circuit simulations and mixed-mode simulations of a CMOS static RAM, two A/D converters, and a phase-locked loop are presented. These results indicate that iSPLICE3 is between one and two orders of magnitude faster than SPICE2 with negligible loss in accuracy     

Statistical Design of Low Power Square-Law CMOS Cells for High Yield

A robust design of low voltage low power square law CMOS composite cells using statistical VLSI design techniques is presented. Since random device/process variations do not scale down with feature size or supply voltage, the statistical design of low voltage circuits is essential in order to keep functional yields of low voltage circuits at levels that are competitive and cost effective. The Response Surface Methodology and Design of Experiment techniques were used as statistical techniques. This article shows that statistical techniques will result in area/layout optimization which will enhance functional yield of low voltage analog ICs.     

Multi-Objective Evolutionary Algorithm Based on Decomposition for Energy Efficient Coverage in Wireless Sensor Networks

Wireless sensor networks (WSNs) have become a hot area of research in recent years due to the realization of their ability in myriad applications including military surveillance, facility monitoring, target detection, and health care applications. However, many WSN design problems involve tradeoffs between multiple conflicting optimization objectives such as coverage preservation and energy conservation. Many of the existing sensor network design approaches, however, generally focus on a single optimization objective. For example, while both energy conservation in a cluster-based WSNs and coverage-maintenance protocols have been extensively studied in the past, these have not been integrated in a multi-objective optimization manner. This paper employs a recently developed multi-objective optimization algorithm, the so-called multi-objective evolutionary algorithm based on decomposition (MOEA/D) to solve simultaneously the coverage preservation and energy conservation design problems in cluster-based WSNs. The performance of the proposed approach, in terms of coverage and network lifetime is compared with a state-of-the-art evolutionary approach called NSGA II. Under the same environments, simulation results on different network topologies reveal that MOEA/D provides a feasible approach for extending the network lifetime while preserving more coverage area.     

Variability aware SVM macromodel based design centering of analog circuits

Design centering is the term used for a procedure of obtaining enhanced parametric yield of a circuit despite the variations in device and design parameters. The process variability in nanometer regimes manifest into variations in these devices and design parameters. During design space exploration of analog circuits, a methodology to find design-instances with better yield is necessitated; this would ensure that the circuit will function as per specifications after fabrication, even with impact of statistical variations. We need to evaluate circuit performance for a given instance of a circuit-design identified by possessing a set of nominal values of device-design parameters. A lot of instances need be searched, having different sizes for a given circuit topology. HSPICE is very compute intensive. Instead, we employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits of different sizing during yield optimization loops. These performance macromodels are found to be as accurate as SPICE and at the same time, time-efficient for use in sizing of analog circuits with optimal yield. Process variability aware SVM macromodels are first trained and then used inside the Genetic algorithm loops for design centering of different circuits, subsequently resulting into sized-circuit instances having optimal yield. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. The application of this design centering approach as process variability analysis tool is illustrated on various circuits e.g. two stage op amp, voltage controlled oscillator and mixer circuit with layouts drawn into 90?nm UMC technology (Euro-practice).     

Low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications

State-of-the-art endoscopy systems require electronics allowing for real-time, bidirectional data transfer. Proposed are 2.4-GHz low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications. The prototype integrates a low-IF receiver analog front-end [low noise amplifier (LNA), double balanced down-converter, bandpass-filtered automatic gain controlled (AGC) loop and amplitude-shift keying (ASK) demodulator], and a direct up-conversion transmitter analog front-end [20-MHz IF phase-locked loop (PLL) with well-defined amplitude control circuit, ASK modulator, up-converter, and power amplifier] on a single chip together with an internal radio frequency oscillator and local oscillating (LO) buffers. Design tradeoffs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low power consumption. The circuits have been implemented in a 0.25-microm CMOS process. The measured sensitivity of the receiver analog front-end is -70 dBm with a data rate of 256 kbps, and the measured output power of the transmitter analog front-end could achieve -23 dBm with a data rate of 1 Mbps. The integrated circuit consumes a current of 6 mA in receiver mode and 5.6 mA in transmitter mode with a power supply of 2.5 V. This paper shows the feasibility of achieving the analog performance required by the wireless endoscopy capsule system in 0.25 microm CMOS.     

NMOS IC's for clock and data regeneration in gigabit-per-secondoptical-fiber receivers

The design and performance of two essential analog circuits in optical-fiber receivers is described. A time-interleaved decision circuit is capable of regenerating 35-mV nonreturn-to-zero (NRZ) data inputs to full logic levels at 1.1 Gb/s with 10^-11 bit error rate (BER), and a phase-locked loop (PLL) extracts the clock from a 2 ²³ long pseudorandom sequence at 1.5 Gb/s with 13-ps r.m.s. jitter. The two circuits have been implemented as 1-μm NMOS ICs, and in their core area dissipate 200 and 350 mW, respectively     

基于模糊C均值聚类的锦标赛选择机制与多目标优化研究

本文提出了一种用于多目标优化的进化算法--基于模糊C均值聚类的进化算法（A Fuzzy C-Means Clustering Based Evolutionary Algorithm,FCEA）.在算法的迭代过程中,先利用模糊C均值聚类算法寻找种群的分布结构,通过对每一代种群进行模糊划分,获得每个个体隶属于每一类的隶属度,然后本文设计了一种基于隶属度的锦标赛选择算子,用于从整个种群中选择相似个体进行重组,引导算法进行搜索.实验结果表明,基于隶属度的锦标赛选择算子的应用能够提升算法的性能,与MOEA/D-DE、NSGAⅡ、SPEA2、SMS-EMOA等先进的优化算法进行比较的结果表明,FCEA在求解具有复杂Pareto前沿的多目标优化问题（GLT系列）时具有一定的竞争力.