Design of Sub-1 mW CMOS LC VCO based on current reused topology with Q-enhancement and body-biased technique

A CMOS LC voltage controlled oscillator (VCO) based on current reused topology with low phase noise and low power consumption is presented for IEEE 802.11a (Seller et al. A 10 GHz distributed voltage controlled oscillator for WLAN application in a VLSI 65 nm CMOS process, in: IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 3–5 June, 2007, pp. 115–118.) application. The chip1 is designed with the tail current-shaping technique to obtain the phase noise −116.1 dBc/Hz and power consumption 3.71 mW at the operating frequency 5.2 GHz under supply voltage 1.4 V. The second chip of proposed VCO can achieve power consumption Sub 1 mW and is still able to maintain good phase noise. The current reused and body-biased architecture can reduce power consumption, and better phase noise performance is obtained through raising the Q value. The measurement result of the VCO oscillation frequency range is from 5.082 GHz to 5.958 GHz with tuning range of 15.8%. The measured phase noise is −115.88 dBc/Hz at 1 MHz offset at the operation frequency of 5.815 GHz. and the dc core current consumption is 0.71 mA at a supply voltage of 1.4 V. Its figure of merit (FOM) is −191 dBc/Hz. Two circuits were taped out by TSMC 0.18 μm 1P6M process.     

Design formula for band-switching capacitor array in wide tuning range low-phase-noise LC-VCO

A low phase noise with wide tuning range complementary LC cross-coupled voltage control oscillator (LC-VCO) using 0.18 μm CMOS technology is presented. This paper proposes a design formula for the choice of the value of varactor (ΔC_var) and band switch capacitor (C_s) for the binary-weighted band-switching LC tank which is convenient to determine the proper tuning constant for wideband, low-phase-noise operations. This general formula considers the ratio of frequency overlap (ov) and all the parasitic effects from band-switching capacitor array and transistors. The designed VCO using a 4-bit band-switching capacitor array demonstrates the operating frequencies from 4.166 to 5.537 GHz with an equivalent tuning bandwidth of 28.26%. The measured tuning range of all sub-bands is well agreed with that of the post-layout simulation results. The measured phase noise is −123.1 dBc/Hz at 1 MHz offset in the 5.2 GHz band. The calculated figure-of-merit (FoM) of this VCO was as high as −187 dB. When considering the tuning bandwidth the designed VCO obtains a FoM-bandwidth product of 52.83, which is much better than previously published works.     

A novel complementary Colpitts differential CMOS VCO with low phase noise performance

A low phase noise Ka-band CMOS voltage-controlled oscillator is proposed in this paper. A new complementary Colpitts structure was adopted in a 0.18-μm CMOS process to achieve differential-ended outputs, low phase-noise performance, and low-power consumption. The designed VCO oscillates from 29.8 to 30 GHz with 200 MHz tuning range. The measured phase noise at 1-MHz offset is −109 dBc/Hz at 30 GHz and −105.5 dBc/Hz at 29.8 GHz. The power consumption of VCO is only 27 mW. In addition, compared with the published papers, the proposed CMOS VCO achieves the best figure of merit (FOM) of −185 dB at 29.95-GHz band.     

Ultra wideband, low-power, 3-5.6 GHz, CMOS voltage-controlled oscillator

In this paper, a low-power inductorless ultra wideband (UWB) CMOS voltage-controlled oscillator is designed in TSMC 0.18 μm CMOS technology as a part of a ultra wideband FM (UWBFM) transmitter. The VCO includes a current-controlled oscillator (CCO) which generates output frequencies between 1.5 and 2.8 GHz and a voltage-to-current (V-to-I) converter. A low-power frequency doubler based on a Gilbert cell, which operates in weak inversion, doubles the VCO tuning range achieving oscillation frequencies between 3 and 5.6 GHz. Thus, the well-known proportionality between the oscillation frequency and the bias tuning current in CCOs is avoided for the entire achieved tuning range, resulting in a lower power design. The employed architecture provides high suppression, over 45 dB, of the 1st and 3rd harmonics, while enabling high-frequency operation and conversion gain due to the unbalanced structure and the single-ended output. The current consumption is 5 mA at a supply voltage of 1.8 V. The VCO exhibits a phase noise of −80.56 dBc/Hz at 1 MHz frequency offset from the carrier and a very high ratio of tuning range (60.4%) over power consumption equal to 8.26 dB which is essential for a UWBFM transmitter.     

宽带低相噪CMOS LC VCO的设计

设计了一款宽带CMOSLCVCO,在分析VCO相位噪声来源的基础上,对VCO进行了结构优化和噪声滤除,并采用了开关电容阵列以增加带宽。电路采用0.18μmCMOS射频工艺进行流片验证,芯片面积为0.4mm×1mm。测试结果显示:芯片的工作频率为3.34～4.17GHz,中心频率为4.02GHz时输出功率是-9.11dBm,相位噪声为-120dBc/Hz@1MHz,在1.8V工作电压下的功耗为10mW。     

一个6GHz宽带低相位噪声CMOS LC VCO

用SMIC 0.13 μm CMOS工艺实现了一个低相位噪声的6 GHz压控振荡器(VCO).在对其相位噪声分析的基础上,通过改进和优化传统的调谐单元和噪声滤波电路以及加入源极负反馈电阻实现了一个宽带、低增益、低相位噪声VCO.测试结果显示,在中心频率频偏1 MHz处的相位噪声为-119 dBc/Hz,频率调谐范围为6...     

Low Voltage CMOS LC VCO with Switched Self‐Biasing

This paper presents a switched self‐biasing and a tail current‐shaping technique to suppress the 1/f noise from a tail current source in differential cross‐coupled inductance‐capacitance (LC) voltage‐controlled oscillators (VCOs). The proposed LC VCO has an amplitude control characteristic due to the creation of negative feedback for the oscillation waveform amplitude. It is fabricated using a 0.13 µm CMOS process. The measured phase noise is ‐117 dBc/Hz at a 1 MHz offset from a 4.85 GHz carrier frequency, while it draws 6.5 mA from a 0.6 V supply voltage. For frequency tuning, process variation, and temperature change, the amplitude change rate of the oscillation waveform in the proposed VCO is 2.1 to 3.2 times smaller than that of an existing VCO with a fixed bias. The measured amplitude change rate of the oscillation waveform for frequency tuning from 4.55 GHz to 5.04 GHz is 131 pV/Hz.     

Low-Phase Noise Hartley Differential CMOS Voltage Controlled Oscillator

This letter presents a novel Hartley low phase noise differential CMOS voltage-controlled oscillator (VCO). The low noise CMOS VCO has been implemented with the TSMC 0.18-mum 1P6M CMOS technology and adopts full PMOS to achieve a better phase noise performance. The VCO operates from 4.02 to 4.5GHz with 11.3% tuning range. The measured phase noise at 1-MHz offset is about -119dBc/Hz at 4.02GHz and 122dBc/Hz at 4.5GHz. The power consumption of the VCO core is 6.75mW     

Design of a 30 GHz rotary traveling wave oscillator with improved frequency tuning range in 0.18 μm CMOS technology

In this paper, the operation of rotary traveling wave oscillators is analyzed, the general oscillation condition is derived, and analytical formula for the oscillator loss is presented. Based on this analysis, switched transmission line is employed to extend the output frequency tuning range. Post-layout simulation shows a frequency tuning range of 3.1 GHz in the vicinity of 30 GHz. The proposed half-quadrature VCO exhibits a phase noise better than −102.2 dBc/Hz at 1 MHz offset frequency. The VCO provides an output power level ranging from −6 to −2.5 dBm with drawing 15.2 mA of dc current from a 1.8 V power supply.     

A cross coupled low phase noise oscillator using an output swing enhancement technique

A new voltage controlled oscillator (VCO) in a 0.18 μm CMOS process is offered in this paper. This paper?s argument is to provide an innovative approach to improve the phase noise which is one of the most controversial issues in VCOs. Contrary to most ideas that have been put forward to decrease phase noise which are based on higher current dissipation to increase output voltage swing, this new method offers better specifications with respect to traditional solutions. The presented circuit is capable of extra oscillation amplitude without increasing the current level, taking advantages of tail current elimination and topology optimization. Analysis of the presented peak voltage amplitude can verify the optimum performance of the proposed. Post-layout simulation results at 2.3 GHz with an offset frequency of 1 MHz and 3 MHz show a phase noise of about −125 dBc/Hz and −136.5 dBc/Hz, respectively, with the current of 1.3 mA from 1.8 V supply. Also, Monte Carlo simulation is used to ensure the sensitivity of the proposed circuit to process and frequency variations are very promising.     

一种LC全集成、具有对称噪声滤波及宽调节范围的4.8GHz CMOS平衡振荡器

将对称噪声滤波技术应用到4.8GHz LC全集成VCO设计中.该VCO具有很低的相位噪声以及716MHz的调节范围,在SMIC 0.25μm单层多晶、五层金属、n阱 RF CMOS工艺上实现,在2.5V电源电压下工作电流仅为6mA,与常规VCO比较,在相同条件下,噪声性能改善了6dBc/Hz.芯片测试结果表明,在偏离4.8GHz载波1MHz的地方相位噪声为-123.66dBc/Hz,该设计在锁相环及其他消费类电子产品中有广泛应用.     

数字电视调谐器中低噪声LC VCO的设计

给出了基于0.25μm CMOS工艺的数字电视调谐芯片中宽带低噪声LC VCO的设计,通过对VCO谐振网络的优化设计,显著抑制了flick噪声对相位噪声的影响,使三个波段的VCO的相位噪声有了明显改善,文中重点讨论了中波段VCO谐振网络的设计方法并给出中波段的相位噪声的仿真和测试结果。结果显示在中波段偏移中心频率10k处的相噪能改善5~10dBc,整个中波段相位噪声低于-85dBc/Hz@10kHz,频率覆盖190~530MHz。     

5-GHz CMOS LC VCOs with wide tuning ranges

A 4.8-GHz LC voltage-controlled oscillator (VCO) optimized for maximum tuning range was designed and fabricated using 0.25-/spl mu/m 1P5M CMOS process. The optimized design used an inverse proportionality between the two parasitic capacitances of the inductor and the MOS transistors for minimizing the parasitic capacitance at the oscillation node. The fabricated LC VCO has a wide tuning range of 20.3% from 4.32 GHz to 5.3 GHz with a power dissipation of 7.3 mW. This tuning range performance is comparable to, or better than, those of the reported CMOS LC VCOs in 5-GHz band. The measured phase noise is -82 dBc/Hz and -114.6 dBc/Hz at 100 KHz and 1-MHz offset, respectively.     

4.2GHz 1.8V CMOS LC压控振荡器

基于Hajimiri提出的VCO相位噪声模型,分析了差分LC VCO电路参数对于相位噪声的影响。根据前面的分析,详细介绍了LC VCO电路的设计方法:包括高Q值片上电感的设计、变容MOS管的设计以及尾电流的选取。采用SMIC 0.18μm 1P6 M、n阱、混合信号CMOS工艺设计了一款4.2GHz 1.8V LC VCO。测试结果表明:当输出频率为4.239GHz时,频偏1MHz处的相位噪声为-101dBc/Hz,频率调节范围为240MHz。     

A low power and low phase-noise 91~96 GHz VCO in 90 nm CMOS

This paper reports a 94 GHz CMOS voltage-controlled oscillator (VCO) using both the negative capacitance (NC) technique and series-peaking output power and phase noise (PN) enhancement technique. NC is achieved by adding two variable LC networks to the source nodes of the active circuit of the VCO. NMOSFET varicaps are adopted as the required capacitors of the LC networks. In comparison with the conventional one, the proposed active circuit substantially decreases the input capacitance (C_in) to zero or even a negative value. This leads to operation (or oscillation) frequency (OF) increase and tuning range (TR) enhancement of the VCO. The VCO dissipates 8.3 mW at 1 V supply. The measured TR of the VCO is 91~96 GHz, close to the simulated (92.1~96.7 GHz) and the calculated one (92.2~98.2 GHz). In addition, at 1 MHz offset from 95.16 GHz, the VCO attains an excellent PN of – 98.3 dBc/Hz. This leads to a figure-of-merit (FOM) of ?188.5 dBc/Hz, a remarkable result for a V- or W-band CMOS VCO. The chip size of the VCO is 0.75 × 0.42 mm², i.e. 0.315 mm².     

Design and Analysis of Varactorless 65 nm MMW Voltage Controlled Oscillator

In this work a novel inductive tuning technique for millimeter wave (mmw) applications is presented. Fine frequency tuning is performed using a transformer. For the LC tanks inductive element, transformer is used. To tune the VCO MOS switch is placed at center tapping of the secondary coil of the transformer. The simulation shows that by changing the operating condition of MOS switch frequency band from 59.1 GHz to 64.6 GHz is obtained. The proposed 60 GHz VCO is designed using UMC 65 nm CMOS single Poly eight Metal (1P8M) Technology. Obtained Frequency Tuning Range (FTR) is 8.89% and the corresponding phase noise variation is from ???112.4 dBc/Hz to ???115.9 dBc/Hz at 10 MHz offset from the carrier. The worst phase noise value is ???112.4 dBc/Hz which is obtained at 0.3 V tuning voltage. For 0.8 V supply voltage 7.44 mW of power is dissipated. And the calculated Figure of Merit (FOM) for whole FTR, ranges from ???179.89 dBc/Hz to ???182.62 dBc/Hz.

     

A 0.18 μm CMOS ring VCO for clock and data recovery applications

In this paper, a 3.125 GHz four stage voltage controlled ring oscillator is presented. The oscillator has been designed in a 0.18 μm CMOS process with a 1.8 V supply. Behavioral simulations predict an 18% tuning range for the oscillator, with −91 dBc/Hz phase noise at 1 MHz offset. Its power consumption has been simulated to be as low as 15.3 mW and the variation of its DC level of oscillation is 20 mV, which corresponds to 1.3% of its mean value. While consuming less area than an LC VCO, the proposed oscillator design achieves a more stable and reliable operation point.     

A 84% tuning range, 4.3-GHz VCO with two-step negative-G<Subscript>m</Subscript> tuning and amplitude calibration loop

This paper presents wideband, low voltage CMOS LC-VCO with automatic two-step amplitude calibration loop to compensate the PVT variation. To cover the wide tuning range, digital automatic negative-G_m tuning loop and analog automatic amplitude calibration loop are proposed. The power consumption is 2–6 mA from a 1.2 V supply. The VCO tuning range is 3.4 GHz, from 2.35 to 5.75 GHz. The measured phase noise is −117 dBc/Hz at the 1 MHz offset when the center frequency is 4.313 GHz.     

A 5-GHz low phase noise differential colpitts CMOS VCO

A low noise 5-GHz differential Colpitts CMOS voltage-controlled oscillator (VCO) is proposed in this letter. The Colpitts VCO core adopts only PMOS in a 0.18-/spl mu/m CMOS technology to achieve a better phase noise performance since PMOS has lower 1/f noise than NMOS. The VCO operates from 4.61 to 5 GHz with 8.3% tuning range. The measured phase noise at 1-MHz offset is -120.42 dBc/Hz at 5 GHz and -120.99 dBc/Hz at 4.61 GHz. The power consumption of the VCO core is only 3 mW. To the authors' knowledge, this differential Colpitts CMOS VCO achieves the best figure of merit (FOM) of 189.6 dB at 5-GHz band.     

使用三位三阶Δ∑调制器的集成1GHz小数频率合成器

本文实现了一个采用三位三阶Δ∑调制器的高频谱纯度集成小数频率合成器.该频率合成器采用了模拟调谐和数字调谐组合技术来提高相位噪声性能,优化的电源组合可以避免各个模块之间的相互干扰,并且提高鉴频鉴相器的线性度和提高振荡器的调谐范围.通过采用尾电流源滤波技术和减小振荡器的调谐系数,在片压控振荡器具有很低的相位噪声,而通过采用开关电容阵列,该压控振荡器达到了大约100MHz的调谐范围,该开关电容阵列由在片数字调谐系统进行控制.该频率合成器已经采用0.18μm CMOS工艺实现,仿真结果表明,该频率频率合成器的环路带宽约为14kHz,最大带内相位噪声约为-106dBc/Hz;在偏离载波频率100kHz处的相位噪声小于-120dBc/Hz,具有很高的频谱纯度.该频率合成器还具有很快的反应速度,其锁定时间约为160μs.