Ultrahigh-speed heterojunction bipolar transistormultiplexer/demultiplexer ICs

High-speed 2-b monolithic integrated multiplexer (MUX) and demultiplexer (DMUX) circuits have been developed using self-aligned AlGaAs/GaAs heterojunction bipolar transistors (HBTs) with improved high-speed performance. Both ICs were designed using emitter-coupled logic. The 2:1 MUX was composed of a D-type flip-flop (D-FF) merging a selector gate and a T-type flip-flop (T-FF). The 1:2 DMUX consisted of two D-FFs driven at a clock of half the rate of the input data. Error-free operation with a pseudorandom pattern was confirmed up to 10 Gb/s. The rise and fall times of the output signals of both ICs were 40 and 25 ps, respectively. HBT frequency dividers were used as inputs for both ICs in order to find the maximum operation speed. Although only a few test patterns were available, the maximum operation speeds of the MUX and DMUX were found to be around 15 and 19 Gb/s, respectively     

A 4 Gbits/s GaAs 16:1 multiplexer/1:16 demultiplexer LSI chip

A GaAs 16:1 multiplexer (MUX)/1:16 demultiplexer (DMUX) LSI chip, which operates at data rates from 50 Mb/s up to 4 Gb/s in a multilayer ceramic package, is described. The LSI chip incorporates trees of 2:1 MUX and 1:2 DMUX. The 2:1 MUX is composed of a master-slave D-flip-flop (DFF) joined with a 2-1 selector. The 1:2 DMUX consists of DFFs which are either a master-slave or the tristage type. The package has 76 pins and consists of five layers, including four power layers, and is applicable up to 7.7 GHz operation. The LSI chip is fabricated using a flat-gate self-aligned implantation for n⁺-layer technology (FG-SAINT process)     

双向波长上下路光分插复用器

通过对科技文献的归纳总结和分析比较,介绍了四种实现双向波长上下路的光分插复用器结构和工作原理,它们是：（1）基于FBG和多口光环形器;（2）基于波导光栅路由器和FBG;（3）基于阵列波导光栅（AWG）;（4）基于解复用器／复用器对和光开关的OADM结构。     

High-speed 8:1 multiplexer and 1:8 demultiplexer implemented withAlGaAs/GaAs HBTs

An 8:1 multiplexer (MUX) and 1:8 demultiplexer (DMUX) implemented with AlGaAs/GaAs heterojunction bipolar transistors are described. The circuits were designed for lightwave communications, and were demonstrated to operate at data rates above 6 Gb/s. These are among the fastest 8-b MUX-DMUX circuits ever reported. Each contains about 600 transistors and consumes about 1.5 W. The pair provides features such as resettable timing, data framing, and clock recovery circuitry, and a built-in decision circuit on the DMUX. Emitter-coupled logic (ECL) compatible input/output (1/O) signals are available. The circuits were implemented with bi-level current mode logic (CML) and require a -5.2-V power supply and a +1-V bias for ECL compatibility     

DWDM系统中的Interleaver技术

目前密集波分复用(DWDM)系统已广泛应用于长途干线、城域网．并扩展至接入网。其中波分复用／解复用器是系统的核心器件之一．而50GHz的密集波分复用更要靠一种交叉波分复用(Interleaver)的全新器件．为此详细阐述了Interleaver的原理、主要实现方案及其特点。     

SCM光通信系统用复合／解复合器的研究

本文介绍了一种用于副载波复用（ｓｕｂｃａｒｒｉｅｒｍｕｌｔｉｐｌｅｘｉｎｇＳＣＭ）光通信系统的副载波复合／解复合器电路组件的结构及设计方法，其中就组件内各子电路的特性分析与设计用基本理论进行了简要叙述。最后给出了典型硬件样品的几组实测特性结果。     

A 12.5 Gb/s Si bipolar IC for PRBS generation and bit errordetection up to 25 Gb/s

This paper describes a Si bipolar IC which features PRBS generation, bit error detection, (de-) scrambling, and trigger derivation up to 12.5 Gb/s. The sequence length is switchable between 2 ¹¹-1 and 2¹⁵-1 b. Two input/output channels are provided which allow PRBS testing up to 25 Gb/s with one external MUX/DMUX. The 3×4 mm², 1377 transistor chip uses 0.4 μm emitter 25-GHz-f_T single-poly self-aligned Si bipolar technology and dissipates 4.6 W from a single -5 V supply     

MMI型1.31/1.55 μm GaAs波分复用/解复用器的研制

利用多模波导的自镜像原理,分析设计了一种能直接与单模光纤相耦合的具有最小循环比的1.31/1.55 μm波长的GaAs/GaAlAs波分复用/解复用器。该器件的输入、输出单模波导和SIE多模波导采用离散谱折射率法进行优化设计,最后获得了当输入、输出单模波导宽为3 μm、SIE多模波导宽度和最佳耦合长度分别为18 μm和5 602.8 μm时,该器件对1.31 μm和1.55 μm两个波长的隔离度均在70 dB以上,且传输损耗小于0.1 dB。     

Accurate modeling of optical multiplexer/demultiplexerconcatenation in transparent multiwavelength optical networks

This paper presents an accurate theoretical model for the study of concatenation of optical multiplexers/demultiplexers (MUXs/DMUXs) in transparent multiwavelength optical networks. The model is based on a semianalytical technique for the evaluation of the error probability of the network topology. The error-probability evaluation takes into account arbitrary pulse shapes, arbitrary optical MUX/DMUX, and electronic low-pass filter transfer functions, and non-Gaussian photocurrent statistics at the output of the direct-detection receiver. To illustrate the model, the cascadability of arrayed waveguide grating (AWG) routers in a transparent network element chain is studied. The performance of the actual network is compared to the performance of a reference network with ideal optical MUXs/DMUXs. The optical power penalty at an error probability of 10^-9 is calculated as a function of the number of cascaded AWG routers, the bandwidth of AWG routers, and the laser carrier frequency offset from the channel's nominal frequency     

A 4-wavelength optical multi/demultiplexer for WDM subscriber loop systems using analog baseband video transmission

This paper describes the design principles and performance of optical multi/demultiplexers (MUX/DEMUX's) in wavelength-division multiplexing (WDM) subscriber-loop systems over a 50- μm core diameter, graded-index (GI), multimode fiber, which employ analog baseband video transmission using laser diodes (LD's). In this WDM arrangement, requirements for MUX/DEMUX's are: 1) low insertion loss; 2) no signal degradation caused by optical interchannel crosstalk; 3) only a small amount of analog baseband signal degradation caused by the use of MUX/DEMUX; 4) a small size and simple structure capable of multiplexing three or four wavelengths; and 5) good stability. The newly developed 4-wavelength MUX/DEMUX satisfies the preceding requirements and is suitable for application to WDM subscriber-loop systems using analog baseband signals along with digital signals.     

GaAs DCFL 2.5 Gbps 16-bit Multiplexer/Demultiplexer LSI's

GaAs 2.5 Gbps 16 bit MUX/DEMUX LSI's have been successfully developed. DCFL is employed as a basic gate in order to reduce the power dissipation. To avoid the speed degradation caused by using DCFL, various technologies such as 8×2(MUX)/2×8(DEMUX) data conversion processes, a Selector Merged Shift Register, clock overlapping, and a 0.7-μm BPLDD MESFET, have been introduced. Moreover the ECL I/O level interface and single power supply features make it easy to use MUX/DEMUX in optical communication systems. The maximum operating data rate is 3.2 Gbps for both LSI's, and the power dissipation of chips which operates with 2.5 Gbps are as low as 1.3 W for each MUX/DEMUX     

0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using currentmode logic with tolerance to threshold voltage fluctuation

A feedback MOS current mode logic (MCML) is proposed for the high-speed operation of CMOS transistors. This logic is more tolerant to the threshold voltage fluctuation than the conventional MCML and is suitable for gigahertz operation of deep-submicron CMOS transistors. Using this logic, 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) ICs for optical-fiber-link systems have been fabricated with 0.18-μm CMOS transistors. The ICs are faster than conventional CMOS MUX and DEMUX ICs and their power consumption is less than 1/4 of that of the conventional 10-Gb/s MUX and DEMUX ICs made using Si bipolar or GaAs transistors     

Expansion of channel number in optical demultiplexer using cascaded photopolymer volume gratings

A method to expand the number of channels in the optical demultiplexer (DMUX) using two cascaded photopolymer volume gratings is proposed and presented. A 0.4-nm-spaced 130-channel DMUX with the channel uniformity of 3.5 dB, the 3-dB bandwidth of 0.12 nm, and the channel crosstalk of -20 dB is experimentally demonstrated.     

SiGe-HBT-based 54-gb/s 4:1 multiplexer IC with full-rate clock for serial communication systems

A 4:1 multiplexer (MUX) IC for 40 Gb/s and above operations in optical fiber link systems has been developed. The ICs are based on 122-GHz-f/sub T/ 0.2-/spl mu/m self-aligned selective-epitaxial-growth SiGe HBT technology. To reduce output jitter caused by clock duty distortion, a master-slave delayed flip-flop (MS-DFF) with full-rate clock for data retiming is used at the final stage of the MUX IC. In the timing design of the critical circuit for full-rate clocking, robust timing design that has a wide timing margin between data and clock at the MS-DFF was achieved. Measurements using on-wafer probes showed that the MUX attained 54-Gb/s operation with an output voltage-swing of 400 mVpp. The output rms jitter generated by the MUX was 0.91 ps and tr/tf (10%-90%) was 11.4/11.3 ps at a data rate of 50 Gb/s. Power consumption of the IC was 2.95 W at a power supply of -4.8 V. Error-free operation (<10/sup -12/) in back-to-back configuration of the MUX and a 1:4 DEMUX IC module at a data rate of 45 Gb/s was confirmed. We therefore concluded that the MUX IC can be applied for transmitter functions in optical-fiber-link systems at a data rate of 40 Gb/s and higher for forward error correction.     

A 150 mW 8:1 MUX and a 170 mW 1:8 DEMUX for 2.4 gb/s optical-fibercommunication systems using n-AlGaAs/i-InGaAs HJFET's

An 8:1 multiplexer (MUX) and a 1:8 demultiplexer (DEMUX) for 2.4-Gb/s optical communication systems have been developed using 0.35-μm GaAs heterojunction field-effect transistors (FETs). To ensure timing margins, a new timing generator with latches and new clock buffers with cross-coupled inverters have been developed. These large-scale integrations (LSIs) operate at over 2.4 Gb/s with a power consumption of 150 mW (MUX) and 170 mW (DEMUX) at a supply voltage of 0.7 V, and at over 5 Gb/s with power consumption of 200 mW at a supply voltage of 0.8 V     

Over 80 Gbit/s 2:1 multiplexer and low power selector ICs using InP/InGaAs DHBTs

A 2:1 multiplexer (MUX) and low power selector ICs have been successfully designed and manufactured using an InP/InGaAs DHBT technology. The 2:1 MUX has been tested at data rates up to 80 Gbit/s with an output swing of 600 mV, while the selector IC has achieved operation speed up to 90 Gbit/s at a power consumption of only 385 mW.     

26GS/s单bit量化降速芯片

基于1μm GaAs HBT工艺设计并实现了一种26GS/s单bit量化降速芯片。芯片采用树形级联架构,集成前端宽带比较器,综合优化各级降速单元拓扑,在功耗、速度各方面达到最优化。测试结果表明,芯片在26GS/s转换速率下,其SFDR大于8dBc,数据带宽达13GHz,显示出其在电子对抗及高速数据处理方面的潜力。     

50-Gb/s 4-b multiplexer/demultiplexer chip set using InP HEMTs

A 50-Gb/s 4:1 multiplexer (MUX) and 1:4 demultiplexer (DEMUX) chip set using InP high electron mobility transistors (HEMTs) is described. In order to achieve wide-range bit-rate operation from several to 50 Gb/s, timing design inside the ICs was precisely executed. The packaged MUX operated from 4 to 50Gb/s with >1-V/sub pp/ output amplitude, and the DEMUX exhibited >180/spl deg/ phase margin from 4 to 50 Gb/s for 2/sup 31/-1 pseudorandom bit sequence (PRBS). Furthermore, 50-Gb/s back-to-back error-free operation for 2/sup 31/-1 PRBS was confirmed with the packaged MUX and DEMUX.     

1 × 2 Wavelength Multiplexer With High Transmittances Using Extraneous Self-Imaging Phenomenon

This paper introduces a wavelength multiplexer (MUX) using the extraneous self-imaging (Ex_SI) phenomenon, which is not mentioned in multimode-interference theory. The Ex_SI phenomenon in silica-based multimode waveguides was experimentally studied. Then, using data for the Ex_SI phenomenon, the wavelength MUX for the wavelengths of 1310 and 1550 nm was developed. The optimum length of the multimode waveguide, with a width of 18 mum, was confirmed as a 3670- mum wavelength MUX. For the wavelengths of 1310 and 1550 nm, the excess losses were determined to be -0.4 and -0.45 dB, respectively, while the extinction ratios were 16.9 and 19.7 dB, respectively     

基于FPGA的高速DMUX设计

介绍了基于Altera公司FPGA的高速DMUX(数据分路器)设计.通过与DMUX专用器件的比较,说明了这种实现方式的优势.