脉冲超宽带系统中的高速低功耗ADC设计

采用TSMC 0.13 μm CMOS工艺,设计并实现了一种适用于脉冲超宽带无线通信系统的低功耗高速单比特模数转换器(ADC)。芯片内部采用并行数据降速输出电路。芯片测试结果表明,该ADC最高采样率为2.5 GS/s,单比特模数转换器最小分辨率为10 mV,芯片核心电路面积为0.72 mm²,在1.2 V电源供电下消耗功耗42 mW。     

基于40 nm工艺的单比特超宽带ADC

采用TSMC 40 nm工艺实现了一款宽带高速ADC。芯片采用时间交织的结构,单通道采用Flash结构,采样率为5 GS/s,8个子通道交织达到40 GS/s的采样率。测试结果表明,芯片的采样率可以达到38.4 GS/s,且在该采样率下,输入信号带宽可达18 GHz,灵敏度小于-20 dBm,可以满足单比特超宽带收发系统的需求。     

微电子所研制成功8GS/s 4bit ADC和10GS/s 8bit DAC芯片

近日,中科院微电子所微波器件与集成电路研究室(四室)超高速电路课题组在超高速ADC/DAC芯片研制上取得突破性进展,成功研制出8GS/s 4bit ADC和10GS/s 8bit DAC芯片。ADC芯片采用带插值平均的Flash结构,集成约1250只晶体管,测试结果表明芯片可以在8GHz时钟频率下稳定工作,最高采样频率可达9GHz。超高速DAC芯片采用基于R-2R的电流开关结构,同时集成了     

基于InP HBT的5 GS/s采样保持电路设计

基于0.7μm、ft=280 GHz的InP HBT工艺设计了一种双开关宽带超高速采样保持电路。芯片面积1.5 mm×1.8 mm,总功耗小于2.1 W。仿真结果表明,电路可以在5 GS/s采样速率下正常工作。当采样速率分别为5 GS/s和1 GS/s时,在输入信号功率为4 d Bm的情况下,采样带宽分别为16 GHz和20 GHz;在输入信号功率为4 d Bm且其频率小于5 GHz的情况下,电路的SFDR分别不低于43 d Bc和50 d Bc。     

基于GaAs HBT工艺的3.8GHz带宽4GS/s 4bit超高速ADC

报道了一种4GS/s 4bit超宽带（UWB）模数转换器（ADC）芯片,采用1.4um发射级宽度、2层金属布线的InGaP/GaAs HBT工艺实现。该芯片采用折叠内插架构来最小化其面积和电路规模。为了消除折叠内插电路中的偶发错误码,该ADC采用了一种新颖的比特同步电路。实测结果表明,其在4GS/s采样率下具有3.8GHz的模拟带宽和2.6GHz的有效精度带宽（ERBW）,在2.6GHz输入带宽内ADC的有效位数大于3.4bit,在4GHz输入带宽内有效位大于3bit。在6.001GHz输入并将输入功率提高4dB后,有效位仍然高达3.49bit,表明该ADC可采样的频率范围包含从第一到第三奈奎斯特区（DC~6GHz）。该芯片的DNL和INL在4GS/s下均小于±0.15LSB,总面积为1.45×1.45 mm2,总功耗为1.98W。     

微电子所成功研制出4GS/s 8位ADC和3GS/s 12位DAC芯片

近日,中科院微电子所微波器件与集成电路研究室(四室)超高速数模混合电路研发团队在超高速模数/数模转换器(ADC/DAC)、直接数字频率合成器(DDS)相关芯片研制上取得重要进展,成功研制出多款高性能芯片。研制成功的芯片包括:4GS/s8位ADC,该芯片由两路ADC交织而成,每路集成宽带采样保持电路并采用优化的折叠内插结构实现。芯片内部集成SPI编程接口,可以有效校准两     

基于FPGA的探地雷达数据采集系统设计

基于探地雷达数据采集系统对数字化集成化的需求,提出了一种基于FPGA的数据采集系统的设计方案,用于采集探地雷达回波信号。FPGA直接通过控制精密延时芯片MC100EP196对采样脉冲进行延时调整,控制采样脉冲的延时步进,系统最大采样率理论值达到100 GS/s,并且时窗可以任意调整。给出了设计方案,对系统的工作原理和特点进行了详细的说明。通过与示波器对比以及分析采集测试效果图,得到稳定有效的数据,实际采样率达到20 GS/s,证明了系统的可行性。     

简讯

力科WavePro954示波器开始供货 WavePro954的带宽为1GHz、4路输入。每路输入的采样率为2GS/s;两路输入交替采样率为4GS/s;单路输入的采样率为8GS/s。每路信号存储长度为250kB。其它指标与Wave     

应用HyperLynx解决高速采集板中阻抗匹配的问题

引言随着数字技术和计算机技术的完善,数字化仪的采样率有很大的提高。目前,已有采样率10GS/s的数字化仪产品,可处理5GHz的模拟信号。数字化仪的采样率提高的根本原因在于AD采样芯片的速度的提高。以AD5463为例,AD5463为12位的AD采样芯片,其采样率可高达500MSPS。随着器件时钟频率日益提高,信号完整性问题变得更加严重。对大多数电子产品而言,当时钟频率超     

低失配GaAs HBT 1.5 bit高速模数转换器设计

介绍了一款基于GaAs HBT工艺的1 GS/s 1.5 bit模数转换器。通过分析模数转换器(ADC)的参考电压失配的来源,引入一种能提高电路对称性的新型差分参考网络架构,提出了减小失配的设计方法,显著提高了参考电平的对称性和一致性,从而减小参考电平的失配。此外,分析了比较器的静态和动态失配电压,对迟滞现象进行了解释。针对ADC的特点,详细分析了新型差分参考网络和比较器的关键设计参数。芯片实测结果表明,片内参考电平失配不超过1 mV,采样频率达到1 GS/s,功耗为350 mW。     

A 4 Gbits/s GaAs 16:1 multiplexer/1:16 demultiplexer LSI chip

A GaAs 16:1 multiplexer (MUX)/1:16 demultiplexer (DMUX) LSI chip, which operates at data rates from 50 Mb/s up to 4 Gb/s in a multilayer ceramic package, is described. The LSI chip incorporates trees of 2:1 MUX and 1:2 DMUX. The 2:1 MUX is composed of a master-slave D-flip-flop (DFF) joined with a 2-1 selector. The 1:2 DMUX consists of DFFs which are either a master-slave or the tristage type. The package has 76 pins and consists of five layers, including four power layers, and is applicable up to 7.7 GHz operation. The LSI chip is fabricated using a flat-gate self-aligned implantation for n⁺-layer technology (FG-SAINT process)     

A 12.5 Gb/s Si bipolar IC for PRBS generation and bit errordetection up to 25 Gb/s

This paper describes a Si bipolar IC which features PRBS generation, bit error detection, (de-) scrambling, and trigger derivation up to 12.5 Gb/s. The sequence length is switchable between 2 ¹¹-1 and 2¹⁵-1 b. Two input/output channels are provided which allow PRBS testing up to 25 Gb/s with one external MUX/DMUX. The 3×4 mm², 1377 transistor chip uses 0.4 μm emitter 25-GHz-f_T single-poly self-aligned Si bipolar technology and dissipates 4.6 W from a single -5 V supply     

A 10-GHz 8-b multiplexer/demultiplexer chip set for the SONETSTS-192 system

An ultrahigh-speed 8-b multiplexer (MUX) and demultiplexer (DMUX) chip set has been developed for the synchronous optical network (SONET) next-generation optical-fiber communication systems, which will require data bit rates of about 10 Gb/s. These ICs were designed using three novel concepts: a tree-type architecture giving reliable operation, a dynamic divider with a wide operating range, and a 50-Ω on-chip transmission line with high-speed pulse propagation. They were fabricated using a 0.5-μm WN_x-gate GaAs MESFET process. The DMUX and MUX operated at up to 10.4 and 11.4 GHz, respectively, both with an adequate phase margin of more than 230°     

单通道8bit1.4GS/s折叠内插ADC

基于0.18 μm CMOS工艺设计并实现了一种8 bit 1.4 GS/s ADC.芯片采用多级级联折叠内插结构降低集成度,片内实现了电阻失调平均和数字辅助失调校准.测试结果表明,ADC在1.4GHz采样率下,有效位达6.4bit,功耗小于480 mW.文章所提的综合校准方法能够有效提高ADC的静态和动态性能,显示出...     

An S‐Band Multifunction Chip with a Simple Interface for Active Phased Array Base Station Antennas

An S‐band multifunction chip with a simple interface for an active phased array base station antenna for next‐generation mobile communications is designed and fabricated using commercial 0.5‐μm GaAs pHEMT technology. To reduce the cost of the module assembly and to reduce the number of chip interfaces for a compact transmit/receive module, a digital serial‐to‐parallel converter and an active bias circuit are integrated into the designed chip. The chip can be controlled and driven using only five interfaces. With 6‐bit phase shifting and 6‐bit attenuation, it provides a wideband performance employing a shunt‐feedback technique for amplifiers. With a compact size of 16 mm² (4 mm × 4 mm), the proposed chip exhibits a gain of 26 dB, a P1dB of 12 dBm, and a noise figure of 3.5 dB over a wide frequency range of 1.8 GHz to 3.2 GHz.     

GaAs PHEMT超宽带六位数控延时器芯片

研究了数控延时器(TTD)芯片的基础原理,基于GaAs PHEMT工艺,设计了一款超宽带数控延时器芯片,该芯片具有超宽带、大延时量和小尺寸等优点,主要用于有源相控阵雷达中。微波在片测试系统对该6位延时器芯片实际测试结果显示,在3~17 GHz范围内,延时调节范围为10~630 ps,64态延时均方根(RMS)误差小于8 ps,全态插入损耗小于22 dB,插损波动小于±1 dB,全频带输入输出电压驻波比(VSWR)小于1.7,整个芯片尺寸仅为4.0 mm×2.6 mm×0.07 mm。实测结果与理论仿真结果吻合良好。     

A 4 GS/s 4 bit ADC with 3.8 GHz analog bandwidth in GaAs HBT technology

An ultra-wideband 4 GS/s 4 bit analog-to-digital converter(ADC)which is fabricated in 2-level interconnect, 1.4μm InGaP/GaAs HBT technology is presented.The ADC has a-3 dB analog bandwidth of 3.8 GHz and an effective resolution bandwidth(ERBW)of 2.6 GHz.The ADC adopts folding-interpolating architecture to minimize its size and complexity.A novel bit synchronization circuit is used in the coarse quantizer to eliminate the glitch codes of the ADC.The measurement results show that the chip achieves larger than 3.4 ENOBs with an input frequency band of DC-2.6 GHz and larger than 3.0 ENOBs within DC-4GHz at 4 GS/s.It has 3.49 ENOBs when increasing input power by 4 dB at 6.001 GHz of input.That indicates that the ADC has the ability of sampling signals from 1st to 3rd Nyquist zones(DC-6 GHz).The measured DNL and INL are both less than±0.15 LSB. The ADC consumes power of 1.98 W and occupies a total area of 1.45×1.45 mm~2.     

一种基于FPGA的超宽带雷达数字接收机

脉冲超宽带雷达回波信号由于带宽大而难以直接采样,文中设计并实现了一种基于FPGA的数字式脉冲超宽带雷达接收机。该接收机利用FPGA内嵌锁相环产生特定频率的时钟,驱动四路10 bit ADC器件,根据回波信号在一段时间内呈准静态及周期性的特点,实现了四通道时域伪随机等效采样。仿真及测试结果表明,该数字式脉冲超宽带雷达接收机等效采样速率可达10 GS/s,可有效接收雷达回波信号,满足脉冲超宽带雷达的应用需求。     

A 1 GHz Digital Channel Multiplexer for Satellite Outdoor Unit

A digital channel multiplexer for satellite outdoor unit running at 1 GHz clock frequency is implemented in 65 nm CMOS mixed oxide dual voltage technology. This multiplexer, based on a 1 GS/s digital signal processor (DSP) approach with 500 MHz input and output bandwidth, embeds two 8 bit 1 GS/s analog-digital converters (ADCs) and two 8 bit 1 GS/s digital-analog converter (DACs). It consumes less that 1022 mW at ambient temperature while achieving noise rejection up to 42.5 dB on a single tone, and > 37 dB on modulated satellite channels.     

A 53mW IQ pipelined ADC for WLAN front end

This paper presents an analog to digital converter (ADC) architecture suitable for wideband wireless receiver system. The in-phase (I) and quadrature (Q) ADCs work independently, but share on-chip reference buffer and non-overlapped clock generation block for balance between two channels. The single ADC core consists of one front sample and hold amplifier, four cascade of 2.5 bit pipeline stages with pseudo-class AB opamp shared between adjacent stages and one 2 bit backend flash stage. The prototype was fabricated in standard 130 nm CMOS process and occupied silicon area of 0.62 mm². Performance of 66 dB spurious-free-dynamic-range is measured at 80 MS/s with 1 Vpp input signal. The power dissipation of the whole chip is only 53 mW from a 1.1 V supply.