一种高性能CMOS单片中频接收机

研制了一种CM O S低压低功耗中频接收机芯片,它包含混频器、限幅放大器、解调器以及场强指示、消音控制等模块,可用于短距离的FM/FSK信号的接收和解调。该接收机采用1st s ilicon 0.25μm CM O S工艺,芯片的测试结果表明整机接收灵敏度为-103 dBm,最高输入射频频率可以达到100 MH z,解调器的线性解调范围为±10 kH z,典型鉴频灵敏度为40 mV/kH z,输入FM信号(调频指数3,信号频率1 kH z)时解调信号的SFDR为41.3 dB。芯片的工作电源电压范围为2~4 V,工作电流3 mA,有效面积0.25 mm2。     

Low-power fully integrated and tunable CMOS RF wireless receiver for ISM band consumer applications

A 0.25-/spl mu/m single-chip CMOS single-conversion tunable low intermediate frequency (IF) receiver operated in the 902-928-MHz industrial, scientific, and medical band is proposed. A new 10.7-MHz IF section that contains a limiting amplifier and a frequency modulated/frequency-shift-key demodulator is designed. The frequency to voltage conversion gain of the demodulator is 15 mV/kHz and the dynamic range of the limiting amplifier is around 80 dB. The sensitivity of the IF section including the demodulator and limiting amplifier is -72 dBm. With on-chip tunable components in the low-power low-noise amplifier (LNA) and LC-tank voltage-controlled oscillator circuit, the receiver measures an RF gain of 15 dB at 915 MHz, a sensitivity of -80 dBm at 0.1% bit-error rate, an input referred third-order intercept point of -9 dBm, and a noise figure of 5 dB with a current consumption of 33 mA and a 2450 /spl mu/m/spl times/ 2450 /spl mu/m chip area.     

A 1.5-V 0.7–2.5-GHz CMOS Quadrature Demodulator for Multiband Direct-Conversion Receivers

An integrated quadrature demodulator with an on-chip frequency divider is reported. The mixer consists of a transconductance stage, a passive current switching stage, and an operational amplifier output stage. A complementary input architecture has been used to increase the transconductance for a given bias current. The circuit is inductorless and is capable of operating over a broad frequency range. The chip was implemented in a 0.13-mum CMOS technology. From 700 MHz to 2.5 GHz, the demodulator achieves 35 dB of conversion voltage gain with 250-kHz IF bandwidth, a double-sideband NF of 10 dB with 9-33 kHz 1/f-noise corner. The measured IIP3 is 4 dBm for a 0.1-MHz IF frequency and 10 dBm for a 1-MHz IF frequency. The total chip draws 20 to 24 mA from a single 1.5-V supply.     

Analysis of delay-and-multiply optical FSK receivers withline-coding and non-flat laser FM response

We present a theoretical analysis of the performance of coherent optical FSK systems when the driving laser signal is AMI or Manchester (biphase) line-coded to counteract the nonideal FM characteristic of the transmit laser diode, and the received signal is heterodyned and detected by a delay-and-multiply demodulator. The analysis takes into account IF filtering by assuming linear filtering of the noisy signal phase, accounting, for small linewidths, for laser phase noise in a straightforward and accurate manner. A simple equivalent baseband model of the system is derived for performance evaluation, applicable to both cases of large demodulator delay and when the delay tends to zero (ideal discriminator). Noise statistics include the clicks due to both signal and phase noise. The problem of performance evaluation is reduced to a classical intersymbol interference problem which is solved by mead of the method of Gauss quadrature rules. The analysis accurately predicts the effectiveness of AMI and Manchester line coding, depending on several system parameters such as linewidth, modulation index, IF bandwidth and laser FM response, and can be easily extended to other line coding techniques     

Automatic Cancellation Method of Multipath Echo Distortion in FM Broadcasting Receivers

An automatic canceling method of multipath echo distortion in FM broadcasting receiver is proposed. The cancelling system is composed of two additional parts to the conventional receiver: a programable transversal filter operating at linear IF stage and a microcomputer. The microcomputer calculates echo parameters (relative echo amplitudes, delay times and phase differences between direct wave and echoes at the carrier frequency), from the amplitude-frequency characteristics between sending station and IF stage of the receiver, which is obtained from both outputs of an IF signal envelope detector and FM demodulator. The microcomputer sends control signals to the weighting circuits of the transversal filter. The output signal of the transversal filter is fed back and added to the incoming signal. Tap weighting adjustment is continued until a flat amplitude-frequency characteristics is obtained. The results of computer simulation show this method works well for various echo conditions and the distortion can be completely eliminated.     

A novel demodulator/detector for digital and analog signals on LMRchannels

The design, implementation, and performance of an all-digital demodulator/detector suitable for differential phase-shift keying (DPSK), continuous-phase frequency-shift keying (CPFSK), frequency-shift keying (FSK), and analog FM are discussed. In this modulator/detector, two detectors, one noncoherent and another differentially coherent, operate simultaneously to provide data detection and automatic frequency control (AFC). Test results indicate that the system provides improved performance over the conventional analog quadrature detector for two-period raised-cosine (2RC) CPFSK modulation in additive white Gaussian noise (AWGN) and Rayleigh fading channels. Being all-digital, the demodulator/detector is well suited for integrated circuit implementation. In addition, the system performs as well as the analog quadrature detector for analog FM voice transmissions, thereby maintaining full compatibility with analog land mobile radio (LMR) transmissions     

A synchronous phase-lock loop detector for integrated AM radio

A synchronous phase-lock loop AM detector has been realized on a single chip in a bipolar process with an f/SUB T/ of 400 MHz. The circuit accepts input signals at an IF frequency of 450-500 kHz with effective values between 20 and 100 mV. The phase-lock loop capture range is about 150 kHz. AM signals with over 80% modulation depth can be demodulated with less than 1% harmonic distortion in the audio output signal. The power dissipation of the chip is 120 mW at 8 V. The total chip size is 1900/spl times/1300 /spl mu/m/SUP 2/. Since the VCO and the 90/spl deg/ phase shift are completely realized on-chip, large signals at the IF frequency do not occur at the pins of the IC, and parasitic feedback of such signals to the IF amplifier input is minimized.     

A VLSI demodulator for digital RF network applications: theory andresults

An all-digital demodulator/detector which is suitable for both analog FM and digital phase/frequency modulations is presented. The system uses complex sampling, which employs a single A/D (analog/digital) converter to sample the signal at an intermediate frequency (IF) and produce baseband in-phase (I) and quadrature phase (Q) signals, and a simplified technique for reducing the effect of the I/Q timing misalignment usually associated with this approach. The system also includes two detectors which operate simultaneously to provide noncoherent and differentially coherent detection, as well as automatic gain control (AGC) and automatic frequency control (AFC). The flexibility afforded by the two concurrent detectors in this all-digital system is shown to make it suitable for a wide range of applications. The theory behind the demodulator/detector system is described, and an implementation using a 1.25-μm bulk CMOS VLSI process is presented. Methods are shown for extending and improving the I/Q sampling misalignment correction technique, as well as for reducing the A/D sampling rate for a given IF frequency. Simulation and experimental results illustrate system performance for both analog and digital modulations     

Unique Positive FM-AM Decomposition of Signals

An analytic signal, observed over an interval of T seconds, is decomposed into a Minimum Phase (AM) and an All-Phase (FM) signal. The former's log-envelope and phase form a Hilbert transform pair while the latter has positive definite instantaneous frequency (IF). An AM-FM demodulator algorithm to achieve the above decomposition is proposed.     

0.18-/spl mu/m CMOS Bluetooth analog receiver with -88-dBm sensitivity

A CMOS Bluetooth analog low-IF receiver that includes a low-noise amplifier, image-rejection mixer, IF bandpass active filter, and programmable gain amplifier (PGA) was fabricated in a 0.18-/spl mu/m bulk CMOS process. In order to achieve good sensitivity and tolerance against blocking signals, operational amplifiers were used in the active filter and PGA, the filter and PGA were interleaved to minimize noise, and an on-chip automatic tuner adjusts the filter frequency. Other features included a feedforward automatic gain control with rapid convergence. When connected to the digital demodulator of a BiCMOS Bluetooth transceiver, -88-dBm sensitivity was measured at 65-mW power dissipation. All blocking signal specifications were also satisfied.     

S/N and error rate evaluation for an optical FSK-heterodyne detection system using semiconductor lasers

Receiving performance is evaluated for an optical FSK-heterodyne detection system in which semiconductor lasers are used as both an FSK transmitter and an independent local oscillator. Noise and error rate are measured under feedback stabilization of IF signal frequency and electrical equalization of semiconductor laser FM modulation frequency characteristics. The minimum received signal power of -44 dBm, which is about 2 dB better than that in IM direct detection, is achieved at a 10^-9error rate for a 200 Mbit/s signal. Excess errors for FSK signals result from frequency broadening of the laser spectrum. Both AM and FM quantum noises in the lasers are primary factors which determine system performance. Error rate characteristics in an optical FSK direct detection system, in which a Michelson interferometer is employed as an optical frequency discriminator, are compared with the above results.     

A low-power 200-MHz receiver for wireless hearing aid devices

The design of a low-power receiver for a wireless hearing aid system working in the 174-223-MHz range and its implementation in a 0.8-/spl mu/m BiCMOS technology is shown. The chip comprises a low-noise amplifier, an RF mixer, a variable-gain IF amplifier, and a demodulator. The latter consists of a digital phase shifter and I/Q IF mixers, fifth-order Bessel filters, and dc amplifiers. Measurements demonstrate that merely 667 /spl mu/A is consumed for the reception of an 8-ary phase-shift keying signal with a data rate of 336 kb/s. The receiver works with different modulation formats, including those carrying information in the amplitude.     

A New Demodulation Method Improving FM System Interference Immunity

As a result of investigation of interference into FM systems, a new algorithm for the process of demodulation is proposed. When compared to the method using the conventional limiter-discriminator, it offers better immunity against the baseband interference noise. Desired signal processing is performed by the functional devices added to the conventional limiter-discriminator in such a way that this new demodulator can be optimized in the sense of the minimum baseband interference noise. The statistics of the wanted and interfering signals must be known. Several examples involving interference problems in FDM-FM radio-relay systems carrying multichannel telephone signals are elaborated to illustrate the performances of the proposed demodulator. FDM-FM, PSK, or FSK systems are considered the cause of the interference. The noise power ratio (NPR) at the output of the conventional limiter-discriminator and the improvement factor offered by the new demodulator, obtained on digital computer, are presented versus baseband frequency in the form of diagrams. Different IF filters in FDM-FM receiver and transmit filters in the interfering systems are taken into account. The improvement offered by the proposed demodulator is of such a degree that some of the important restrictions in planning different radio systems could be relaxed.     

Distance limits of 10 to 20 Gbit/s FSK transmission on standardfibre

A simple analysis is performed on an FSK transmission system using a high FM efficiency, high bandwidth DFB laser as a simple DFB transmitter and an FM/AM converter as an optical signal processor. It shows that optimum optical processing pushes the transmission limits to 150 km at 10 Gbit/s and to 40 km at 20 Gbit/s     

A 77-GHz Phased-Array Transceiver With On-Chip Antennas in Silicon: Receiver and Antennas

In this paper, we present the receiver and the on-chip antenna sections of a fully integrated 77-GHz four-element phased-array transceiver with on-chip antennas in silicon. The receiver section of the chip includes the complete down-conversion path comprising low-noise amplifier (LNA), frequency synthesizer, phase rotators, combining amplifiers, and on-chip dipole antennas. The signal combining is performed using a novel distributed active combining amplifier at an IF of 26 GHz. In the LO path, the output of the 52-GHz VCO is routed to different elements and can be phase shifted locally by the phase rotators. A silicon lens on the backside is used to reduce the loss due to the surface-wave power of the silicon substrate. Our measurements show a single-element LNA gain of 23 dB and a noise figure of 6.0dB. Each of the four receive paths has a gain of 37 dB and a noise figure of 8.0 dB. Each on-chip antenna has a gain of +2 dBi     

A mixed-signal GFSK demodulator for Bluetooth

A discrete-time mixed-signal Gaussian frequency-shift keying demodulator designed for a low intermediate frequency Bluetooth receiver performs FSK demodulation. Employing passive sampling and time-domain differentiation techniques, the demodulator performs quadrature demodulation while tolerating up to 200-kHz frequency offset. A distributed array of interleaved sampling circuits and a low-voltage multiplier allow both low-voltage operation and low power dissipation. Fabricated in a CMOS 0.25-/spl mu/m technology, the demodulator only dissipates 6 mW from a 2-V power supply.     

1.2 Gb/s closely-spaced FDMA-FSK direct-detection star network

For the frequency-division-multiple-access-frequency-shift-keying (FDMA-FSK) network, the FSK signal is converted to amplitude-shift-keyed (ASK) format by a tunable fiber Fabry-Perot (FFP) filter that acts simultaneously as a demodulator and demultiplexer. Frequency-tunable two-electrode distributed-feedback (DFB) laser transmitters produce distorted FSK spectra due to nonuniform FM response for modulation frequencies above ~200 Mb/s. The frequency-domain properties of the laser are related directly to the time-domain properties of the transmitted data stream. The critical dependence on the FFP passband width and center frequency location for undistorted signal recovery is shown. By optimizing these parameters, the data transmission rate can be increased while keeping the power penalty due to signal distortion below 1 dB     

A 2-V 10.7-MHz CMOS limiting amplifier/RSSI

This paper presents low-voltage low-power CMOS circuit design techniques for an intermediate frequency (IF) limiting amplifier and received signal strength indicator (RSSI). The architecture of the limiting amplifier and RSSI employed is determined by the optimal power consumption for a specified speed, overall gain, and accuracy. Each gain cell of the limiting amplifier employs folded diode load for low-voltage operation. Offset is reduced by a cross-connected source-coupled pair offset subtractor that is along the signal path. Full-wave current rectification and summation are employed in the RSSI circuit to achieve high precision while maintaining low voltage and low power. Using a single 2-V supply voltage, measured results demonstrate the input dynamic range is larger than 75 dB for 10.7-MHz IF application. The prototype occupies an active area of 0.4 mm² using a 0.6-μm digital CMOS technology. The power dissipation is 6.2 mW     

Clock and data recovery IC for 40-Gb/s fiber-optic receiver

The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gb/s. We report a 40-Gb/s CDR fabricated in indium-phosphide heterojunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in turn, reduces the circuit complexity (transistor count) and the voltage-controlled oscillator (VCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an external demultiplexer, and low-frequency PLL control loop and on-chip limiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.     

A 1.6-GHz CMOS PLL with on-chip loop filter

A 1.6-GHz phase locked loop (PLL) has been fabricated in a 0.6-μm CMOS technology. The PLL consists of an LC-tank circuit, divider, phase detector with charge pump, and an on-chip passive loop filter. When the oscillator is open loop, it exhibits -115 dBc/Hz phase noise at a 600-kHz offset from the carrier. The PLL occupies an active area of 1.6 mm² and dissipates 90 mW from a single 3-V supply