卫星广播电视技术讲座：第五讲 卫星电视接收机（下）

四、调频解调器由于调频制比调幅制抗干扰能力强,故在卫星电视广播中,电视信号对高频载波采用了调频制。调频改善系数I_(FM)定义为调频接收机解调后的信噪比S/N与解调前载噪比C/N之比。即I_(FM)=(S/N)/(C/N)=1.47(Δf_m~2B)/(f_h~3)式中,Δf_m为信号的最大频偏;B为中频滤波器的通频带;f_h为鉴频器后低通滤波器的最高频率,一般设计成f_h为电视视频信号的最高频率成分。由上式可见,f_h愈低(以不低于视频信号的最高频率为限度),Δf_m愈宽,B愈大,则调频改善度愈好,这正是调频制的优点。但是,要获得这种改善度有个前提,就是接收机输入端的载波信号必须远大于混入噪声中的载波幅度,否则调频解调器的抗干扰性能会显著变坏。     

一种FSK数字解调器的结构与芯片设计

设计了一种基于高性能频移键控(FSK)数字解调器的无线鼠标接收方芯片,该芯片整合了无线解调电路和接口控制电路,能够自动识别PS/2和USB接口。解调器采用一种新颖的全数字方案,包括抽取滤波器、数字锁相环(DPLL)、位时钟恢复和自动频率控制(AFC)等部分,可用于频移键控信号的解调。芯片采用SMIC0.35μmCMOS工艺流片,测试结果表明,解调器性能在Eb/No=8dB时,误码率为10-3,接收机灵敏度为-102dBm,同步范围≤±4.9%Rb(Rb为系统数据速率),AFC范围≤±32%Rb,这些特性完全符合无线鼠标接收机的要求。     

注入锁相式门扩电路

卫星电视广播一般均采用调频制,这主要由于频率调制相对于振幅调制具有较强的抗干扰性能。在相同的输入载噪比情况下能够得到较大的输出信噪比(即有较大的制度增益)。这对于卫星发射功率有限,距离地面接收站十分遥远来说,有尤其重要的意义。调频改善因子,即调频解调时的制度增益为: K_(FM)=输出信噪比/输入载噪比若取Δf=m_fF_m可得:K_(FM)=3m_f~3。式中,Δf为解调器前接收机带宽的一半,F_m为调频信号基带最高频率,m_f为调频指数。由于通常m_f>1所以调频信号鉴频解调后输出信噪比较解调前载噪比会有较大提高。     

SB62320MHz调幅解调器

由信息产业部电子第二十四研究所研制的SB62320MHz调幅解调器由调幅解调、AGC放大和SSB解调三部分组成,可广泛应用于AM/SSB接收机、收音机、电视机和通讯机中作解调器。SB623的主要性能参数包括:工作频率10～30MHz,解调输出幅度≥100mVp-p,频率响应50Hz～50kHz,电源电流≤13mA。该电路具有以下特点:1)滤波电容外接实现;2)输入小信号时AGC放大级处于截止状态,满足自动增益控制的范围;3)输入大信号时,AGC处于工作状态;4)AM检波器与SSB单边带检波器不同时工作,防止信号干扰;5)输出音频信号频率响应与滤波电容相关;6)SSB输出幅度…     

基于变长观察法载波同步的OQPSK全数字解调器

在应用于非协同通信的自适应盲接收机系统中,OQPSK信号的解调是一个难点。本文通过对数字同步技术的研究,提出了一种新的OQPSK全数字解调器。该解调器能够在恶劣信号条件下对OQPSK信号进行解调,对Eb/N0、载波频偏、时钟偏差等有很大的宽容度。本文在解调器数字锁相环的研究中提出了“变长观察法”,很好地解决了数字锁相环频率捕捉范围和相位稳定度对观察长度不同要求之间的矛盾,从而显著扩大了低Eb/N0 条件下数字锁相环的频率捕捉范围。     

新产品

<正> ADI 公司为下一代蜂窝与宽带无线应用提供直接变频接收机解决方案日前,Analog Devices.Inc 最新推出正交解调器与双通道增益调整放大器 ADL5380和 AD8366,用于下一代蜂窝3G/4G 以及宽带无线802.16应用中的直接变频接收机。ADL5380解调器是业界首款能够工作在400MHz～6GHz 的产品,在不同频率的无线电应用中,设计人员采用相同的器件即可。采用 ADL5380解调器,可以满足多种蜂窝和宽带无线数据系统要求,符合 CDMA、W—CDMA、TD-SCDMA、PHS、LTE 与WiMAX 标准。由于工作频率范围和解调带宽较宽,ADL5380也是包括软件无线电在内的国防与航空电子设备的理想解决方案。AD8366已为信号增益控制与精度而优化,提供0.25dB 精密微调步进分辨率的自动     

16GHz CMOS4∶1分频器

采用TSM C 0.18μm标准CM O S工艺实现了一种4∶1分频器。测试结果表明,电源电压1.8 V,核心功耗18 mW。该分频器最高工作频率达到16 GH z。当单端输入信号为-10 dBm时,具有5.8 GH z的工作范围。该分频器可以应用于超高速光纤通信以及其它高速数据传输系统。     

带有振幅闭环控制的PLL的研究

本文旨在研究带有振幅闭环控制的锁相环A—PLL对AM、FM及AM/FM信号的解调及再生性能。计算机模拟及电路实验的结果表明,A—PLL能够解调和再生AM、FM及AM/FM信号,因而可将其用作AM/FM解调器或构成带有振幅闭环控制的交叉耦合锁相环A—CCPLL。     

调频立体声接收机FM 4S

电子调谐式FM立体声接收机FM—4S以高品质、高灵敏度为设计目标,调整点极少。基板按框图分割,既容易理解。又便于装配。 电路的整体结构图1为整个电路的框图。图2为调谐头。图3为FM—IF MPx电路。图4是电源电路。 本机的主块采用三洋电机的PLL FMMPX解调器LA3361,它最适合于便携式收音机、汽车收音机等低电源工作的调频立体声解调用,工作电压范围为3V～16V,功耗     

解调FM信号的波形发生器

图1所示电路采用了精密波形发生器IC的相位检测器信号来实现FM(调频)的解调。在一种标准的应用场合,IC的相位检测器输入和输出使芯片的输出频率与外加信号的频率实现同步。如果信号是调频的,你就能从相位输出器的输出中提取解调的信号。波形发生器IC的相位检测器输入(PDI)一般接收锁相信     

A 10.7-MHz IF-to-baseband ΣΔ A/D conversion system forAM/FM radio receivers

ΣΔ modulation with integrated quadrature mixing is used for analog-to-digital (A/D) conversion-of a 10.7-MHz IF input signal in an AM/FM radio receiver. After near-zero IF mixing to a 165 kHz offset frequency, the I and Q signals are digitized by two fifth-order, 32 times oversampling continuous-time ΣΔ modulators. A prototype IC includes digital filters for decimation and the shift of the near-zero-IF to dc. The baseband output signal has maximum carrier-to-noise ratios of 94 dB in 9 kHz (AM) and 79 dB in 200 kHz (FM), with 97 and 82 dB dynamic range, respectively. The IM3 distance is 84 dB at full-scale A/D converter input signal. Including downconversion and decimation filtering, the IF A/D conversion system occupies 1.3 mm² in 0.25-μm standard digital CMOS. The ΣΔ modulators consume 8 mW from a 2.5-V supply voltage, and the digital filters consume 11 mW     

Low-power fully integrated and tunable CMOS RF wireless receiver for ISM band consumer applications

A 0.25-/spl mu/m single-chip CMOS single-conversion tunable low intermediate frequency (IF) receiver operated in the 902-928-MHz industrial, scientific, and medical band is proposed. A new 10.7-MHz IF section that contains a limiting amplifier and a frequency modulated/frequency-shift-key demodulator is designed. The frequency to voltage conversion gain of the demodulator is 15 mV/kHz and the dynamic range of the limiting amplifier is around 80 dB. The sensitivity of the IF section including the demodulator and limiting amplifier is -72 dBm. With on-chip tunable components in the low-power low-noise amplifier (LNA) and LC-tank voltage-controlled oscillator circuit, the receiver measures an RF gain of 15 dB at 915 MHz, a sensitivity of -80 dBm at 0.1% bit-error rate, an input referred third-order intercept point of -9 dBm, and a noise figure of 5 dB with a current consumption of 33 mA and a 2450 /spl mu/m/spl times/ 2450 /spl mu/m chip area.     

A 2-V CMOS 455-kHz FM/FSK demodulator using feedforward offsetcancellation limiting amplifier

This paper presents a low-voltage low-power IF 455-kHz signal processor that contains a three-stage limiting amplifier and an FM/FSK demodulator. The limiting amplifier uses an on-chip feedforward offset cancellation circuit. The FM/FSK demodulator employs a quadrature detector that is composed of an on-chip phase detector and an external tank phase shifter. The demodulation constant is 20 mV/kHz with masimum ±10-kHz frequency deviation. The IF signal processor that consumes 2.3 mW from a single 2-V power supply demonstrates a high sensitivity of -72 dBm. It occupies an active area of 0.2 mm² using 0.6-μm digital CMOS technology     

A 1.2 mW RDS receiver for portable applications

A 0.9 V 1.2 mA fully integrated radio data system (RDS) receiver for the 88-108 MHz FM broadcasting band is presented. Requiring only a few external components (matching network, VCO inductors, loop filter components), the receiver, which has been integrated in a standard digital 0.18 /spl mu/m CMOS technology, achieves a noise figure of 5 dB and a sensitivity of -86dBm. The circuit can be configured and the RDS data retrieved via an I/sup 2/C interface so that it can very simply be used as a peripheral in any portable application. A 250 kHz low-IF architecture has been devised to minimize the power dissipation of the baseband filters and FM demodulator. The frequency synthesizer consumes 250 /spl mu/A, the RF front-end 450 /spl mu/A while providing 40 dB of gain, the baseband filter and limiters 100 /spl mu/A, and the FM and BPSK analog demodulators 300 /spl mu/A. The chip area is 3.6 mm/sup 2/.     

A CMOS MF energy harvesting and data demodulator receiver for wide area low duty cycle applications with 250 mV start-up voltage

A low voltage start-up energy harvesting medium frequency receiver is presented, for use as the power and synchronisation part of a remote sensor node in a wide area industrial or agricultural application. The use of embedded low bandwidth network synchronisation data permits very low operational duty cycle without the need for real time clocks or wake up receivers at each node with their associated continuous power drain. The receiver consists of a rectifier, a power management unit and a phase-shift keying demodulator. The rectifier is optimised for low start-up and operating voltage rather than power efficiency. With standard MOS thresholds the rectifier can cold start with only 250 mV peak antenna input, and useful battery charging is delivered with 330 mV peak input. The QPSK demodulator consumes 1.27 μW with a supply voltage of 630 mV at a data rate of 1.6 kbps with 1 MHz carrier frequency. The IC is implemented in a standard threshold 0.18 μm CMOS technology, occupies 0.54 mm² and can deliver 10.3 μW at 3 V to an external battery or capacitor.     

High-performance RF mixer and operational amplifier BiCMOS circuits using parasitic vertical bipolar transistor in CMOS technology

The electrical characteristics of the parasitic vertical NPN (V-NPN) BJT available in deep n-well 0.18-/spl mu/m CMOS technology are presented. It has about 20 of current gain, 7 V of collector-emitter breakdown voltage, 20 V of collector-base breakdown voltage, 40 V of Early voltage, about 2 GHz of cutoff frequency, and about 4 GHz of maximum oscillation frequency at room temperature. The corner frequency of 1/f noise is lower than 4 kHz at 0.5 mA of collector current. The double-balanced RF mixer using V-NPN shows almost free 1/f noise as well as an order of magnitude smaller dc offset compared with CMOS circuit and 12 dB flat gain almost up to the cutoff frequency. The V-NPN operational amplifier for baseband analog circuits has higher voltage gain and better input noise and input offset performance than the CMOS ones at the identical current. These circuits using V-NPN provide the possibility of high-performance direct conversion receiver implementation in CMOS technology.     

低压工作的轨到轨输入／输出缓冲级放大器

本文提出了一种低压工作的轨到轨输入／输出缓冲级放大器。利用电阻产生的输入共模电平移动,该放大器可以在低于传统轨到轨输入级所限制的最小电压下工作,并在整个输入共模电压范围内获得恒定的输入跨导;它的输出级由电流镜驱动,实现了轨到轨电压输出,具有较强的负载驱动能力。该放大器在CSMCO．6-μmCMOS数模混合工艺下进行了HSPICE仿真和流片测试,结果表明：当供电电压为5V,偏置电流为60uA,负载电容为10pF时,开环增益为87．7dB,功耗为579uw,单位增益带宽为3．3MHz;当该放大器作为缓冲级时,输入3VPP10kHz正弦信号,总谐波失真THD为53．2dB。     

A low power, low noise figure quadrature demodulator for a 60 GHz receiver in 65-nm CMOS technology

This paper presents the design of a low power (LP) and a low noise figure (NF) quadrature demodulator with an on-chip frequency divider for quadrature local oscillator (LO) signal generation. The transconductance stage of the mixer is implemented by an AC-coupled self-bias current reuse topology. On-chip series inductors are employed at the gate terminals of the differential input transconductance stage to improve the voltage gain by enhancing the effective transconductance. The chip is implemented in 65-nm LP CMOS technology. The demodulator is designed for an input radio frequency (RF) band ranging from 10.25 to 13.75 GHz. A fixed LO frequency of 12 GHz down-converts the RF band to an intermediate frequency (IF) band ranging from DC to 1.75 GHz. From 10 MHz to 1.75 GHz the demodulator achieves a voltage conversion gain (VCG) ranging from 14.2 to 13.2 dB, and a minimum single-sideband NF (SSB-NF) of 9 dB. The measured third-order input intercept point (IIP₃) is -3.3 dBm for a two-tone test frequency spacing of 1 MHz. The mixer alone draws a current of only 2.5 mA, whereas the complete demodulator draws a current of 7.18 mA from a 1.2 V supply. The measurement results for a frequency divider, which was fabricated individually, prior to being integrated with the quadrature demodulator, in 65-nm LP CMOS technology, are also presented in this paper.     

A Universal UHF RFID Reader IC in 0.18-µm CMOS Technology

A highly integrated UHF RFID reader IC in 0.18-m CMOS process covering the entire 860 MHz to 960 MHz RFID band supporting the EPCglobaltrade Class-1 Generation-2 and ISO-18000-6A/B/C standards is presented. The IC features a transmitter with an output of 10 dBm and a receiver with sensitivity of 96 dBm in listen-before-talk mode (LBT) and 85 dBm in talk-mode. Direct-conversion architecture is used for the receiver for a high level of integration and low power consumption. On-chip dual-loop synthesizer generates high-purity LO signal with frequency resolution of 50 kHz and phase noise of 101 dBc/Hz at 100 kHz offset over the entire 860 to 960 MHz band. The IC integrates 10-bit DACs, pulse-shaping filters, an IQ modulator and a power amplifier in the transmit chain and a low-noise amplifier (LNA), an IQ downconverter, channel-select filters, variable-gain amplifiers and 10-bit ADCs in the receive chain. On-chip ASK demodulator provides demodulated I and Q raw data outputs. The chip has a die area of 6 mm times 6 mm. It operates over a wide range of voltage and temperature, from 1.6 V to 2.0 V and from C to C and consumes 540 mW from a 1.8 V supply at C.     

Micro-power low-offset instrumentation amplifier IC design for biomedical system applications

This work presents a micro-power low-offset CMOS instrumentation amplifier integrated circuit with a large operating range for biomedical system applications. The equivalent input offset voltage is improved using a new circuit technique of offset cancellation that involves a two-phase clocking scheme with a frequency of 20 kHz. Channel charge injection is cancelled by the symmetrical circuit topology. With the wide-swing cascode bias circuit design, this amplifier realizes a very high power-supply rejection ratio (PSRR), and can be operated at single supply voltage in the range between 2.5-7.5 V. It was fabricated using 0.5-/spl mu/m double-poly double-metal n-well CMOS technology, and occupies a die area of 0.2 mm/sup 2/. This amplifier achieves a 160-/spl mu/V typical input offset voltage, 0.05% gain linearity, greater than 102-dB PSRR, an input-referred rms noise voltage of 45 /spl mu/V, and a current consumption of 61 /spl mu/A at a low supply voltage of 2.5 V. Experimental results indicate that the proposed amplifier can process the input electrocardiogram signal of a patient monitoring system and other portable biomedical devices.