Sub-100 nm ALD-assisted nanoimprint lithography for realizing vertical organic transistors with high ON/OFF ratio and high output current

We introduced a conformal atomic-layer-deposited aluminum oxide layer to cover the imprint mold to reduce the feature size and to strengthen the mold durability. A nano-hole array pattern with diameter down to 85 nm was successfully transferred to sample substrate to fabricate a vertical organic transistor. The Imprint vertical organic transistor exhibited high output current density as 4.35 cm²/V s and high ON/OFF current ratio as 11,000 at a low operation voltage as 1.5 V.     

Effective mobility in amorphous organic transistors: Influence of the width of the density of states

The temperature dependence of poly(3-hexylthiophene-2,5-diyl) (P3HT)/polystyrene (PS) blend organic transistor current/voltage (I–V) characteristics has been experimentally and theoretically studied. The planar transistors, realized by drop casting the P3HT/PS ink, exhibit high mobilities (over 5 × 10⁻³ cm² V⁻¹ s⁻¹) and good overall characteristics. A transistor model accounting for transport mechanisms in disordered organic materials was used to fit the measured characteristics. Using a single set of parameters, the measured effective mobility versus gate bias, either increasing or decreasing with the gate bias depending on temperature, is well reproduced over a wide temperature range (130–343 K). A Gaussian density of states width of 0.045 eV was determined for this P3HT/PS blend. The transistor I–V characteristics are very well described considering disordered material properties within a self-consistent transistor model.     

Soldering of solution-processed organic vertical transistor and light-emitting diode on separate glass substrates by tin micro-balls

The vertical organic space-charge-limited transistor made of P3HT and small-molecule phosphorescent organic light-emitting diode (OLED) are made on two separate glass substrate by blade coating, then soldered vertically together by tin balls with 40 μm diameter. The soldering is done by hot wind of 150 °C for 5 min Contact resistance is only 10 Ω. The vertical transistor is annealed at 150 °C for 5 min before soldering to enhance the output current up to 25 mA/cm² and give high thermal stability. Both OLED and the annealed vertical transistor are not affected by the soldering process. The vertical transistor has 1/4 of the OLED area and turns on the bottom-emission white OLED up to 300 cd/m² and orange OLED up to 600 cd/m². The entire operation is within 8 V. OLED and transistor array can therefore be made on separate glass substrates then soldered together to form the display.     

Vertical structure permeable-base hybrid transistors based on multilayered metal base for stable electrical characteristics

In this work we present a permeable-base transistor consisting of a 60 nm thick N,N′-diphenyl-N,N′-bis(1-naphthylphenyl)-1,1′-biphenyl-4,4′-diamine layer or a 40 nm thick 2,6-diphenyl-indenofluorene layer as the emitter, a Ca/Al/Ca multilayer as the metal base, and p-Si as collector. In the base, the Ca layers are 5 nm thick and the Al layer was varied between 10 and 40 nm, the best results obtained with a 20 nm thick layer. The devices present common-base current gain with both organic layer and silicon acting as emitter, but there is only observable common-emitter current gain when the organic semiconductor acts as emitter. The obtained common-emitter current gain, ～2, is independent on collector-emitter voltage, base current and organic emitter in a reasonable wide interval. Air exposure or annealing of the base is necessary to achieve these characteristics, indicating that an oxide layer is beneficial to proper device operation.     

Improvement in the on/off ratio of a vertical-type metal-base organic transistor by heat treatment in air

The on/off ratio of a vertical-type metal-base organic transistor was significantly improved by subjecting it to heat treatment in air. The heat treatment of the collector layer and the base electrode reduced the off current that is mainly due to leakage current between the base and the collector, resulting in a considerable decrease in the off current. As a result, a high on/off ratio greater than 10⁵ was achieved, in addition to the low-voltage and high current operation of the vertical-type organic transistor.     

Organic photodetector with built-in amplification for the detection of visible light with low optical power

We report on an organic-based photodetector that integrates a dual-gate organic thin-film transistor (DG-OTFT) with an organic photodiode (OPD) to produce a device with a high effective responsivity at low optical power and video-rate compatible response. In this device, the OPD operates in photovoltaic mode, instead of the commonly used photoconductive mode, to modulate one of the gate voltages of the DG-OTFT. Effective responsivity values of 10 A W⁻¹ are measured at optical power values lower than 10 nW at 635 nm. Modeling of the operation of this new photodetector suggests that effective responsivity values up to 10⁵ A W⁻¹ can be achieved at optical powers of 1 nW using current printing technology and state-of-the-art organic semiconductors.     

Vertical organic-inorganic hybrid transparent oxide TFTs gated by biodegradable electric-double-layer biopolymer

Vertical organic-inorganic hybrid oxide-based electric-double-layer (EDL) thin-film transistors (TFTs) are successfully demonstrated. Low-cost biodegradable chitosan biopolymer is proposed as an efficient EDL electrolyte dielectric in such vertical transparent TFTs. The device is completely transparent in the range of visible light and the whole fabrication process is completed at room temperature. It exhibits a good performance with a large output current of ∼8 mA/cm², a large current on/off ratio of ∼10⁵, a small subthreshold swing of 0.33 V/dec, and a low operation voltage of only 2 V, respectively. Moreover, an energy band diagram based on vertical EDL modulation is proposed to understand the device mechanism. Such vertical organic-inorganic hybrid transistor with a vertical channel may be very promising for some important applications in the state-of-the-art low-cost portable transparent flexible electronics.     

Organic nonvolatile memory devices utilizing intrinsic charge-trapping phenomena in an n-type polymer semiconductor

Charge trapping is an undesirable phenomenon and a common challenge in the operation of n-channel organic field-effect transistors. Herein, we exploit charge trapping in an n-type semiconducting poly (naphthalene diimide-alt-biselenophene) (PNDIBS) as the key operational mechanism to develop high performance, nonvolatile, electronic memory devices. The PNDIBS-based field-effect transistor memory devices were programmed at 60 V and they showed excellent charge-trapping and de-trapping characteristics, which could be cycled more than 200 times with a current ratio of 10³ between the two binary states. Programmed data could be retained for 10³ s with a memory window of 28 V. This is a record performance for n-channel organic transistor with inherent charge-trapping capability without using external charge trapping agents. However, the memory device performance was greatly reduced, as expected, when the n-type polymer semiconductor was end-capped with phenyl groups to reduce the trap density. These results show that the trap density of n-type semiconducting polymers could be engineered to control the inherent charge-trapping capability and device performance for developing high-performance low-cost memory devices.     

Photoreactive π-conjugated star-shaped molecules for the organic field-effect transistor

A number of semiconducting organic molecules capable of wet processing exhibit high carrier mobility and current modulation. In this work, we synthesized photopatternable π-conjugated star-shaped molecules and characterized their physical properties. The solubility of the synthesized molecules is very good for solution processing. The synthesized organic semiconducting multi-branched molecules are capable of photopatterning by virtue of photopolymerization of the reactive pentadienyl end groups. The transistor devices using these molecules provided a field-effect mobility of 1.3(±0.2) × 10^?3–3.7(±0.5) × 10^?3 cm² V^?1 s^?1 as well as a high current on/off ratio (I_on/off > 10³) and a low threshold voltage. In the case of the photoreactive star-shaped conjugated molecule HP2P, it was found that field-effect mobility was maintained even after the photocrosslinking process. This result can be used in the design of photopatternable semiconductor molecules for thin-film transistor electronic applications.     

High-performance solution-processed polymer space-charge-limited transistor

We demonstrate a polymer non-field-effect transistor in a vertical architecture with an Al grid embedded in a polymer sandwiched between another two electrodes. The Al grid containing high density of self-assembled submicron openings is fabricated by a non-lithography method. This device modulates the space-charge-limited current of a unipolar polymer diode with the Al grid. The operating voltage of the device is as low as 4 V, the on/off ratio is higher than one hundred, and the current gain is 10⁴. The current density is higher than 1 mA/cm².     

To observe bidirectional negative differential resistance at room temperature by narrowing transport channels for charge carriers in vertical organic light-emitting transistor

Bidirectional negative differential resistance (NDR) at room temperature with high peak-to-valley current ratio (PVCR) of ～10 are observed from vertical organic light-emitting transistor indium-tin oxide (ITO)/N,N′-di(naphthalene-1-yl)-N,N′-diphenyl-benzidine) (α-NPD)(60 nm)/Al(30 nm)/α-NPD(60 nm)/tris-(8-hydroxyquinoline) aluminium (Alq₃)(50 nm)/Al by narrowing the transport channels for charge carriers with a thick-enough middle Al gate electrode layer to block charge carriers transporting from source electrode to drain electrode. When the transport channel for charge carriers gets large enough, the controllability of gate bias on the drain–source current gets weaker and the device almost works as an organic light-emitting diode only. Therefore, it provides a very simple way to produce NDR device with dominant bidirectional NDR and high PVCR (～10) at room temperature by narrowing transport channels for charge carriers in optoelectronics.     

Low-operating-voltage polymeric transistor with solution-processed low-k polymer/high-k metal-oxide bilayer insulators

We have successfully demonstrated a polymeric semiconductor-based transistor with low-k polymer/high-k metal-oxide (TiO₂) bilayer as gate dielectric. The TiO₂ layers are readily processable from solution and cured at low temperature, instead of traditionally sputtering or high temperature sintering process, thus may suitable for a low-cost organic field effect transistors (FETs) manufacture. The low-k polymer capped on TiO₂ layer could further smooth the TiO₂ dielectric surface and suppress the leakage current from grain boundary of TiO₂ films. The resulting unpatented P3HT-OFETs could operate with supply voltage less than 10 V and the mobility and threshold voltage were 0.0140 cm²/V s and 1.14 V, respectively. The on/off ratio was 1.0 × 10³.     

Contact-Barrier Free,High Mobility,Dual-Gated Junctionless Transistor Using Tellurium Nanowire

The gate-all-around nanowire transistor, due to its extremely tight electrostatic control and vertical integration capability, is a highly promising candidate for sub-5 nm technology nodes. In particular, the junctionless nanowire transistors are highly scalable with reduced variability due to avoidance of steep source/drain junction formation by ion implantation. Here a dual-gated junctionless nanowire p-type field effect transistor is demonstrated using tellurium nanowire as the channel. The dangling-bond-free surface due to the unique helical crystal structure of the nanowire, coupled with an integration of dangling-bond-free, high quality hBN gate dielectric, allows for a phonon-limited field effect hole mobility of 570 cm² V⁻¹ s⁻¹ at 270 K, which is well above state-of-the-art strained Si hole mobility. By lowering the temperature, the mobility increases to 1390 cm² V⁻¹ s⁻¹ and becomes primarily limited by Coulomb scattering. The combination of an electron affinity of ≈ 4 eV and a small bandgap of tellurium provides zero Schottky barrier height for hole injection at the metal-contact interface, which is remarkable for reduction of contact resistance in a highly scaled transistor. Exploiting these properties, coupled with the dual-gated operation, we achieve a high drive current of 216 μA μm⁻¹ while maintaining an on-off ratio in excess of 2 × 10⁴. The findings have intriguing prospects for alternate channel material based next-generation electronics.     

Flexible air-stable three-dimensional polymer field-effect transistors with high output current density

Flexible air-stable short-channel polymer organic field-effect transistor (OFET) arrays with high saturated output current density are demonstrated by utilizing a novel solution-processed naphthobisthiadiazole (NTz) based donor–acceptor semiconducting polymer (PNTz4T) and designing a three-dimensional vertical channel structure with an extremely large ratio of channel width to channel length. The saturated mean field-effect mobility of 0.16 cm²/V s of the short-channel polymer devices remains over one month resulting in air-stable OFET arrays with high on/off ratio over 10⁶ and powerful current–density exceeding 0.3 A/cm² under low operation voltage, both of which meet the requirements for such applications as driving organic light-emitting diodes in active-matrix displays.     

Quantification of temperature rise in unipolar organic conductors during short voltage-pulse excitation using electrical testing methods

To quantify the rise in device temperature caused by Joule heating during short voltage-pulse excitation at high current densities (>10 A/cm²), the device temperatures of unipolar organic conductors were measured using electrical testing methods. For a maximum voltage amplitude of 59 V at a current density of ∼300 A/cm², temperature rose over 145 °C within a pulse duration of 5 μs in an N,N'-di(1-naphthyl)-N,N'-diphenylbenzidine (α-NPD)-based single-carrier organic conductor. This result is in reasonable agreement with numerically calculated values. These findings indicate that suppressing the effects of Joule heating by carefully adjusting pulse width, substrate and organic materials, and device configuration is important to achieve further carrier injection in the ultra-high current density region (>1 kA/cm²).     

n-Al0.15Ga0.85 N/p-6H–SiC heterostructure and based bipolar transistor

Heterojunction bipolar transistor (HBTs) based on Al0.15Ga0.85 N/6H–SiC heterojunction was fabricated. Room-temperature current–voltage (I–V) characteristics of n-Al0.15Ga0.85 N/p-6H–SiC emitter–base heterojunction exhibited good rectifying behavior with a forward current 5 × 10⁻² A and reverse current 3 × 10⁻⁹ A at 10 V and −10 V, respectively. Analysis of the temperature dependent I–V characteristics of this heterojunction revealed a barrier height of 1.1 eV. The fabricated n-Al0.15Ga0.85 N/p-SiC/n-SiC bipolar transistor did not exhibit common-emitter operation, however, common-base operation was observed with current gain β = IC/IB ranging in 75–100.     

2D Short-Channel Tunneling Transistor Relying on Dual-Gate Modulation for Integrated Circuits Application

With continuous size scaling, the surface dangling bonds and short-channel effects will degrade silicon based transistor performance. Thus, it is of great importance to seek new channel materials and transistor architectures to further continue Moore's law. Herein, a new ultra-thin short-channel tunneling transistor is developed comprising all 2D- components. Distinct from usual 2D planar transistor, this device is configured with vertical MoS₂/WSe₂ junction and in-plane WSe₂ channel, the switch states are realized by the gate-regulated barrier height of heterojunction, enabling the transition of transport mechanism between thermionic-emission and tunneling. Under dual-gate configuration, the transistor exhibits high performance with drive current of 4.58 µA, on/off ratio of 4 × 10⁷, subthreshold swing (SS) of 97 mV decade⁻¹ and drain-induced barrier lowering (DIBL) of 12 mV V⁻¹, that can meet the requirement of logical applications in integrated circuits (IC). Taking advantage of the high-speed tunneling current and unique short-channel architecture, the device overcomes the issues of voltage spikes and long reverse recovery time that exist in usual electric components, and thus gains an access to the IC interface. This work provides a proof-of-concept transistor architecture relying on dual-gate modulation, opening up a promising perspective for next generation low-power, high-density, and large-scale IC technologies.     

Bottom gate organic thin-film transistors fabricated by ultraviolet transfer embossing with improved device performance

Ultraviolet transfer embossing is optimized to fabricate bottom gate organic thin-film transistors (OTFTs) on flexible plastic substrates, achieving significant improved device performance (μ = 0.01–0.02cm²/Vs; on/off ratio = 10⁴) compared with the top gate OTFTs made previously by the same method (μ = 0.001–0.002 cm²/Vs; on/off ratio = 10²). The performance improvement can be ascribed to the reduced roughness of the dielectric-semiconductor interface (R_rms = 0.852 nm) and thermally cross-linked PVP dielectric which leads to reduced gate leakage current and transistor off current in the bottom-gated configuration. This technique brings an alternative great opportunity to the high-volume production of economic printable large-area OTFT-based flexible electronics and sensors.     

An analytical model for the epitaxial bipolar transistor

In the n⁺pn^?n⁺ transistor, high-current effects in the base and collector regions are linked within the current ranges of practical interest. To describe such effects, we have derived an analytical model that is based primarily on five assumptions: (1) the structure is approximately one-dimensional; (2) recombination is negligible in the base and collector quasi-neutral regions, and in the three space-charge regions; (3) high-current effects are negligible in the emitter and n⁺-substrate regions; (4) the Fletcher boundary conditions (or the Misawa boundary conditions) can be used for the three space-charge regions; and (5) the ambipolar approach can be used for the base and collector quasi-neutral regions. The primary findings predicted by the n⁺pn^?n⁺ transistor model are: In current ranges of practical interest (usable current gain), the electron concentration profile has a significant “vertical step” located at the collector-base metallurgical junction for all values of collector current. In the limit of extremely-high-current operation, this step tends to vanish. In the current range where the current gain begins to decline rapidly with increasing collector current, the electron concentration at the base boundary of the collector-base space-charge region goes approximately as the square of the hole concentration at the collector boundary of the same region. Because of this relationship, a charge-control calculation is more difficult than a straightforward calculation of carrier concentration for a given degree of accuracy. The n⁺pn^?n⁺ transistor model (which consists of twelve algebraic equations) is particularly useful for the practically important case of an epitaxial bipolar transistor having a very thin, heavily-doped base region.     

Investigation of deep level defects in copper irradiated bipolar junction transistor

Commercial bipolar junction transistor (2N 2219A, npn) irradiated with 150 MeV Cu¹¹⁺-ions with fluence of the order 10¹² ions cm^?2, is studied for radiation induced gain degradation and deep level defects. I–V measurements are made to study the gain degradation as a function of ion fluence. The properties such as activation energy, trap concentration and capture cross-section of deep levels are studied by deep level transient spectroscopy (DLTS). Minority carrier trap levels with energies ranging from E_C ? 0.164 eV to E_C ? 0.695 eV are observed in the base–collector junction of the transistor. Majority carrier trap levels are also observed with energies ranging from E_V + 0.203 eV to E_V + 0.526 eV. The irradiated transistor is subjected to isothermal and isochronal annealing. The defects are seen to anneal above 350 °C. The defects generated in the base region of the transistor by displacement damage appear to be responsible for transistor gain degradation.