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开关型词组电动机调速系统(Switched Reluctance Drive,简称SRD)是80年代中期发展起来的新型交流调速系统,它融新的电动机结构——开关型磁阻电动机(简称SR电动机)与现代电力电子技术,控制技术为一体,兼有异步电动机变频调速系统和直流电动机调速系统的优点,已成为当代电气传动的热门课题之一。 相似文献
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本文讨论了高频开关式交流斩波电路的工作原理与电路调压控制技术,交流斩波调压控制技术是一种新型高性能的交流调压技术,在中小交流调压领域获得广泛应用。本文通过对开关反串联式斩波调压电路的原理分析,对比了三相三管交流斩波调压电路和单相单管交流斩波调压电路的控制方式,并对电路的扩展功能的新技术进行了探讨。 相似文献
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基于FPGA直流电机调速器的实现 总被引:3,自引:0,他引:3
近年来,直流电动机的结构和控制方式都发生了很大变化。随着计算机进入控制领域以及新型的电力电子功率元件的不断出现,使采用全控型的开关功率元件进行脉宽调制PWM控制方式已成为主流。同时,随着可编程门阵列器件FPGA的出现,给直流调速控制提供了新的手段和方法。这种控制方式很容易在FPGA控制中实现,从而为直流电动机控制数字化提供了契机。本文简要介绍了直流电动机的控制策略和直流电动机的PWM调压调速原理。详细介绍了可编程门阵列器件(FPGA)及其在直流电机控制系统中的应用。FPGA的使用简化了系统结构,提高了系统工作的稳定性和可靠性。本系统利用硬件描述语言VHDL设计在片内实现电机控制逻辑,包括分频模块、数据锁存模块、比较模块、选择模块等。在Quartus Ⅱ上软件仿真和实验结果均表明输出波形稳定、精确。 相似文献
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对开关磁阻电动机(SRD)的运行控制策略进行了比较,提出了一套适用于SRD的电动摩托车系统的控制策略,实验表明,提出的控制策略达到了理想的效果。 相似文献
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为对开关磁阻电机调速进行实时控制,设计了一款基于DSP的TMS320F2812数字信号处理器为控制核心,设计开发了开关磁阻电机调速系统。以模块化的思想设计了MCU控制系统、位置检测系统、不对称功率电路等模块。给出了软件设计的思想和方法,完成了嵌入式软件系统的开发。该调速系统结构简单、成本低廉、起动转矩大及调速范围宽等优点,具有很好的发展前景。 相似文献
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本文简介了开关磁阻电动机调速系统在钢铁厂高炉助燃风机的应用, 开关磁阻电动机调速系统以其优越的调速性能、显著的节能效果、简单的结构特征,越来越多地应用在工业及民用的各领域,被发改委列为国家鼓励发展的技术. 相似文献
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QPSK作为一种先进的数字调制方式,特别适用于数字卫星通信系统。而近年来DSP,FPGA等数字芯片的高速发展,使全数字式调制得到广泛应用。介绍一种适用于卫星通信,基于FPGA,采用QPSK全数字式调制的中频信号发生器的硬件设计方案,给出了工作原理和系统组成、主要元器件说明、以及电路板设计和制作中若干注意事项。 相似文献
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A carrier recovery circuit implementation with an all-digital reverse modulation approach for coherent detection in the GSM/GMSK system as well as the GMSK compatible improved efficiency cross-correlated FQPSK system is presented. The proposed carrier recovery implementation utilizes all-digital reverse modulation circuit in a feedback loop to remove the modulated signal from the received intermediate frequency (IF) signal and to estimate the phase error of this carrier signal using a phase-locked loop (PLL). The digital reverse modulation approach avoids the multipliers required in an analog reverse modulation design, so that it can be implemented in a single chip FPGA. Hardware implementation of the coherent detection demonstrates that cross-correlated FQPSK is completely compatible with GMSK in the system performance and the receiver structure for GSM. Experimental performance evaluations show that the proposed carrier recovery circuit provides a Bit Error Rate (BER) performance within 0.3 dB in a non-linearly amplified channel corrupted by additive white Gaussian noise (AWCN) as compared with the simulated performance of the GSM/GMSK system 相似文献
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Blaabjerg F. Kjaer P.C. Rasmussen P.O. Cossar C. 《Power Electronics, IEEE Transactions on》1999,14(3):563-572
This paper proposes a method to avoid current feedback filters in fast digital-based current loops in switched reluctance drives. Symmetrical pulsewidth modulation (PWM) and synchronized sampling of the phase current allow a noise-free current sampling with no antialiasing filter. This paper also proposes more efficient methods to chop the two transistors in the asymmetric inverter used with switched reluctance drives. A fast field-programmable gate array (FPGA)-based test system is used for validation of the new methods. Test results show a significant improvement in dynamic and steady-state current loop control compared with traditional methods. The new chopping method is found to reduce the switching losses and increase the drive efficiency 相似文献
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介绍了一种基于Xilinx公司FPGA开发工具System Generator进行全数字Costas锁相环的设计仿真方法。通过对Costas锁相环原理的分析,从离散域变换阐述了环路参数的计算及电路设计,基于对CORDIC算法设计DDS的讨论,利用FPGA实现了设计,最后全面分析了环路性能。 相似文献
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针对现有基于PLLs/DLLs的全数字化同步倍频器结构存在的不足,本文提出了基于一种双环结构的全数字同步倍频器。它由延迟锁相环和锁频环共享一个共同的参考时钟信号(FREF)构成,不需要任何模拟组件。它可以采用Verilog-HDL语言设计,可在Altera DE2-70开发板上实现合成,而且可以很容易地适应于不同的FPGA系列以及作为一个集成电路实现,同时也可用于为分布式数字处理系统以及片上系统的片内/片间通信提供时钟参考;实验结果表明,本文所提出的结构相比于现有的结构,能够获得更高频率的输出时钟信号,提供更好的频率分辨率、更好的抖动性能和高倍乘因子。 相似文献
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Two energy-efficient converter topologies, derived from the conventional C-dump converter, are proposed for switched reluctance motor (SRM) drives. The proposed topologies overcome the limitations of the conventional C-dump converter, and could reduce the overall cost of the SRM drive. The voltage ratings of the dump capacitor and some of the switching devices in the proposed converters are reduced to the supply voltage (Vdc) level compared to twice the supply voltage (2V dc) in the conventional C-dump converter. Also, the size of the dump inductor is considerably reduced. The converters have simple control requirements, and allow the motor phase current to freewheel during chopping mode. Simulation and experimental results of the converters are presented and discussed 相似文献
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An all-digital background calibration technique for timing mismatch of Time-Interleaved ADCs (TIADCs) is presented. The timing mismatch is estimated by performing the correlation calculation of the outputs of sub-channels in the background, and corrected by an improved fractional delay filter based on Farrow structure. The estimation and correction scheme consists of a feedback loop, which can track and correct the timing mismatch in real time. The proposed technique requires only one filter compared with the bank of adaptive filters which requires (M-1) filters in a M-channel TIADC. In case of a 8 bits four-channel TIADC system, the validity and effectiveness of the calibration algorithm are proved by simulation in MATLAB. The proposed architecture is further implemented and validated on the Altera FPGA board. The synthesized design consumes a few percentages of the hardware resources of the FPGA chip, and the synthesized results show that the calibration technique is effective to mitigate the effect of timing mismatch and enhances the dynamic performance of TIADC system. 相似文献