基于安全控制边界单元的IP核测试封装方法

为了解决测试信息传递的问题,IEEE组织推出了IEEE1500 IP(Intellectual Property)核测试封装标准以标准化口核测试接口.然而该标准给出的典型测试封装存在由测试数据扫描移人造成的不安全隐患.本文提出了一种基于安全控制边界单元的IP核测试封装方法.这种方法的核心思想是在典型的测试封装边界单元的...     

扫描电路测试功耗综述

随着集成电路制造技术的发展.高集成度使得测试时的功耗成为集成电路设计必须考虑的一个重要因素,低功耗测试也就成为了测试领域一个令人关注的热点.目前,低功耗测试技术的研究还在发展之中,工业生产中低功耗测试方法还没有得到充分的应用.在集成电路中采用扫描结构的可测试性设计方法,能够提高测试覆盖率.缩短测试时间,已在集成电路测试中得到大量应用.基于扫描结构的数字集成电路,学术界已提出了许多方法降低该电路的测试功耗,本文对此方面的研究进行综述.随着测试技术的发展,测试功耗的理论也将日益深入.     

数字IP核的IEEE Std1500外壳架构设计研究

IP核可测试性架构的多样性、互不兼容性给SoC的测试带来不便,IEEE Std1500针对此问题提出了一种标准的、可配置的可测试性架构,如何设计实现这种架构便成为SoC测试研究的热点问题.基于IEEE Std1500,利用边界扫描技术,结合自行设计的IP核,本文给出标准化架构的设计过程,利用quartus ii平台仿真验证了多种测试指令下设计的有效性.提出的外壳并行配置设计打破传统串行测试的局限性,为实现SoC中IP核的并行测试、缩短测试时间提供新的思路.     

基于差值二次分配的扫描链平衡算法

 IP核的测试时间与其加载测试封装后的最大输入/输出扫描链长度有直接关系,为了降低测试成本,减少测试时间,必须对IP核内的扫描链进行平衡设计.最为经典的扫描链平衡方法是BFD(Best Fit Decrease)方法,它具有实现简单、算法复杂度低等优点,但是其分配的结果尚有待提高之处.本文提出一种基于差值的二次分配的扫描链平衡方法,其主要思想是选择IP核内部的某一条扫描链作为基准扫描链,将其长度记为L,将所有长度超过L的扫描链与之做差,并将差值记为di.在第一次分配中,只将长度大于L的扫描链按照长度为L的基准扫描链进行分配;然后将长度小于L的扫描链与差值di重新排序后,按照从大到小的顺序,依次将其放置在可以放置的最小的测试封装扫描链上进行第二次分配.该方法简单易实现,通过在ITC'02 SOC标准测试集上实验,数据表明,基于差值二次分配的扫描链平衡方法与现有方法相比,能得到更好的平衡结果.     

一种可应用于并发在线测试的扫描单元设计

航天等领域对集成电路可靠性要求较高,要求其具有在线测试功能,以便及时发现故障,减少损失。结合现有扫描设计方法,设计了一种改进的扫描单元结构。将该扫描单元应用于时序电路后,能够在电路工作的同时进行测试;通过灵活的时钟选择机制,方便地控制电路进行非并发和并发测试。仿真实验表明,应用本文提出的扫描单元,时序电路能够在增加一定硬件冗余的条件下实现在线测试,时间开销较小,有较高的可靠性和一定的容错能力,实用性强。     

基于IEEE Std1500标准的互连检测构架设计

摘要：随着电路系统向着高密度、高速度的方向发展,引发了严重的信号完整性问题。针对串扰故障,MT故障检测模型具有较好的故障覆盖率,但也存在含有大量矢量冗余的问题。通过对传统MT故障模型的精简,提出了一种新的串扰故障检测模型—改进型MT模型。模型对种子进行筛选及施加,测试矢量有规律跳变,产生了全部的测试矢量。通过对基于IEEE Std 1500标准的IP核测试壳各部分进行设计,特别是对测试环单元进行设计,实现了改进型MT模型故障检测。设计的IP核测试壳能够对IP核与核间互连线进行串行测试和并行测试。通过quartus ii平台仿真及数据计算,验证了该测试构架的有效性和故障检测的高效性。     

基于部分扫描的低功耗内建自测试

在分析全扫描内建自测试 (BIST)过高测试功耗原因的基础上 ,提出了一种选择部分寄存器成为扫描单元的部分扫描算法来实现低功耗 BIST。实验表明 ,提出的方法在保证测试覆盖率的条件下能同时降低 BIST的峰值功耗和平均功耗 ,降幅分别高达 46%和 69%。     

误码测试IP核的设计

提出了一种误码测试IP核的设计方案,可嵌入通信系统,作为系统自检单元的一部分完成系统的误码测试。通过IP核内置的异步串行接口,计算机可以对IP核进行参数配置,并读取误码数据进行性能分析。文中介绍了误码测试IP核结构和关键技术的实现,最后给出了计算机上测试软件的开发方法。     

具备兼容性和层次性的SOC测试控制结构设计

IP核的集成问题是SOC设计的关键,测试集成更是无法回避的难题.因此,灵活高效的测试控制结构成为SOC可测性设计的重要研究内容.文章分析了IEEE Std 1149.1对传统IC芯片内部和外部测试的整体控制能力;剖析了IEEE Std 1500TM对嵌入式IP核测试所做规定的标准性和可配置性.在此基础上,提出了一种复用芯片级测试控制器的测试控制结构,该结构能兼容不同类型的IP核,并且有助于实现复杂SOC的层次性测试控制.     

6端口CMOS寄存器堆设计

高性能超标量处理器完成多条指令并行,需要寄存器堆提供多端口、高速访问.本文介绍一个0.18μmCMOS工艺下的四读二写6端口寄存器堆的全定制设计,它采用改进的多端口存储器单元结构和基于NAND结构的低功耗译码器,并且设计了内部时钟生成部件来提高工作频率.寄存器堆通过功能验证和性能测试,可以工作在450MHz频率上,功耗为36mW,面积0.06mm2,参考综合结果具有高速、低功耗和面积小的特点.     

Test infrastructure design for mixed-signal SOCs with wrapped analog cores

Many system-on-chips (SOCs) today contain both digital- and analog-embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transistor-level simulations for an analog wrapper and a representative core. We present experimental results for three SOCs from the ITC '02 test benchmarks that have been augmented with three analog cores: an I-Q transmit path pair and an audio CODEC path used in cellular phone applications.     

A Reconfigurable Power Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling

The increasing test application times required for testing system-on-chips (SOCs) is a problem that leads to higher costs. For modular core based SOCs it is possibly to employ a concurrent test scheme in order to lower the test application times. To allow each core to be tested as a separate unit, a wrapper is inserted for each core, the scan chains at each core are configured into a fixed number of wrapper chains, and the wrapper chains are connected to the test access mechanism. A problem with concurrent testing is that it leads to higher power consumption as several cores are active at a time. Power consumption above the specified limit of a core or above the limit of the system will cause damage and must be avoided. The power consumption must be controlled both at core level as well as on system level. In this paper, we propose a reconfigurable power conscious core wrapper that we include in a preemptive power constrained test scheduling algorithm. The advantages with the wrapper are that the number of wrapper chains at each core can dynamically be changed during test application and the possibility, through clock gating, to select the appropriate test power consumption for each core. The scheduling technique produces optimal solutions in respect to test time and selects wrapper configurations in a systematic manner while ensuring the power limits at core level and system level are not violated. The wrapper configurations are selected such that the number of wrapper configurations as well as the number of wrapper chains at each wrapper are minimized, which minimizes the wrapper logic as well as the total TAM routing. We have implemented the technique and the experimental results show the efficiency of our approach. The research is supported by the Swedish Foundation on Strategic Research (SFS) under the Strategic Integrated Electronic Systems Research (STRINGENT) program.     

Multiple-Constraint Driven System-on-Chip Test Time Optimization

The cost of testing SOCs (systems-on-chip) is highly related to the test application time. The problem is that the test application time increases as the technology makes it possible to design highly complex chips. These complex chips include a high number of fault sites, which need a high test data volume for testing, and the high test data volume leads to long test application times. For modular core-based SOCs where each module has its distinct tests, concurrent application of the tests can reduce the test application time dramatically, as compared to sequential application. However, when concurrent testing is used, resource conflicts and constraints must be considered. In this paper, we propose a test scheduling technique with the objective to minimize the test application time while considering multiple conflicts. The conflicts we are considering are due to cross-core testing (testing of interconnections between cores), module testing with multiple test sets, hierarchical conflicts in SOCs where cores are embedded in cores, the sharing of the TAM (test access mechanism), test power limitations, and precedence conflicts where the order in which tests are applied is important. These conflicts must be considered in order to design a test schedule that can be used in practice. In particular, the limitation on the test power consumption is important to consider since exceeding the system's power limit might damage the system. We have implemented a technique to integrate the wrapper design algorithm with the test scheduling algorithm, while taking into account all the above constraints. Extensive experiments on the ITC'02 benchmarks show that even though we consider a high number of constraints, our technique produces results that are in the range of results produced be techniques where the constraints are not taken into account.     

Testing analogue and mixed-signal integrated circuits by weighted sum of selected node voltages

System-on-chip (SOC) design based on intellectual property (IP) cores has become a growing trend in integrated circuit (IC) design. Testing of such cores is a challenging problem, especially when these cores are deeply embedded in the system chip. The wrapper of the P1500 standard can facilitate the testing of such cores; however, a full-size wrapper is expensive because the hardware overhead is large. If the requirement for testing I/O pins of IP cores is considered and reduced to a minimum during the core design, SOC designers will need to put much less effort into testing the cores. In this paper, a built-in self-test (BIST) technique, which is applicable to both analogue and mixed-signal integrated circuits and is based on the weighted sum of selected node voltages, is proposed. Besides high fault coverage, the proposed BIST technique needs only one extra testing output pin, and only a single dc stimulus is needed to feed at the primary input of the circuit under test (CUT). Hence, the proposed BIST technique is especially suitable for testing IP cores.     

A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips

This paper deals with the design of SOC test architectures which are efficient with respect to required ATE vector memory depth and test application time. We advocate the usage of a TestRail Architecture, as this architecture, unlike others, allows not only for efficient core-internal testing, but also for efficient testing of the circuitry external to the cores. We present a novel heuristic algorithm that effectively optimizes the TestRail Architecture for a given SOC by efficiently determining the number of TestRails and their widths, the assignment of cores to the TestRails, and the wrapper design per core. Experimental results for four benchmark SOCs show that, compared to previously published algorithms, we obtain comparable or better test times at negligible compute time.     

IPRM: IP core resource multiplexing of core wrapper design for reducing test application time in DVFS-based multicore SoCs

A modify wrapper/test access mechanism(TAM) structure is described to explore the maximal potential capacity of TAM, named “IP cores resource multiplexing(IPRM)”, reducing test application time for DVFS-based multicore System-on-Chips(MSoCs). The IPRM core wrappers, different from standard wrappers, enable to isolated core wrapper resource again to store test data for embedded cores under test. An integer linear programming (ILP) formulation with IPRM wrapper is proposed to improve multi-site test. Experimental results of the ITC’02 SoC Benchmark show that IPRM core wrapper reduces the burdens on ATE effectively, and can reduce the test application time by 10–50%.     

面向SOC设计的可变规模的LCD驱动lP核的设计

文章介绍了一个面向SOC设计的可变规模的LeD驱动IP核,该IP包括四个独立的LeD驱动单元（DU）。不仅可以通过配置该IP使四个独立的Du分别驱动不同规模的LCD,而且能够实现四个Du级联来面对更复杂的应用场合。此外,设计了一个与wishbone总线相兼容的接口模块wrapper,并将该IP结合wrapper模块嵌入到0R1200平台来进行系统级的仿真验证。仿真结果表明该IP达到了设计要求,且通过修改wrapper模块可使该IP核适用于不同的SOC设计平台。     

ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips

Complex system-on-a-chip (SOC) designs usually consist of many memory cores. Efficient yield-enhancement techniques thus are required for the memory cores in SOCs. This paper presents an infrastructure intelligent property (IIP) for testing, diagnosing, and repairing multiple memory cores in SOCs. The proposed IIP can perform parallel testing for multiple memories, and serial diagnosis or repair for one memory each time. In the repair mode, the proposed IIP can execute various redundancy analysis algorithms. Therefore, the user can select a better redundancy analysis algorithm for each memory core being tested according to its redundancy structure. Simulation results show that the proposed IIP needs less test time and redundancy analysis time than the processor-based built-in self-repair scheme. We also have realized the proposed IIP for four types of memories - two 8 K 64 bit SRAMs, one 4 K x 16 bit SRAM, and one 2 K x 32 bit SRAM - based on TSMC 0.18-mum standard cell technology. Simulation results show that the area overhead of the IIP is only about 4.6%.     

复用NoC测试IP芯核测试存取链优化配置

论述了层次型IP芯核不同测试模式之间的约束关系,给出了层次型IP芯核的测试壳结构,提出了一种复用片上网络测试内嵌IP芯核的启发式测试存取链优化配置方法.该方法可有效减小测试数据分组数量和被测芯核的测试时间.使用片上网络测试平台,在测试基准电路集ITC'02中的基准电路p22810上进行了实验验证.