高速FIR滤波器的流水线结构

通过一个13阶线性相位的平方根升余弦滚降FIR数字滤波器的结构设计，介绍了如何应用流水线技术来设计高速FIR滤波器。考虑到FPGA的容量问题，对采用流水线技术之后的FIR滤波器占用的硬件资源进行了分析，得出一些结论。     

高阶平方根升余弦滚降滤波器的FPGA实现

以数字电视解调端256阶平方根升余弦滚降(SRRC)滤波器的设计为例,比较了直接型和转置型高阶FIR滤波器的FPGA实现,分析了两种滤波器结构各自的优缺点.     

平方根升余弦滚降FIR数字滤波器的设计

本文采用本地查找算法，根据不同的误差准则设计了一系列平方根升余弦滚降FIR滤波器，并且在基带传输系统中对FIR滤波器进行了性能仿真，得出了在对称度准则下设计的FIR滤波器具有较好的性能的结论。     

两种成形滤波器抗时钟抖动性能的仿真与分析

介绍了升余弦和平方根升余弦两种成形滤波器,通过Matlab对成形滤波器码间串扰量的数学模型进行了仿真,并分析了升余弦和平方根升余弦滤波器的抗时钟抖动性能.     

窗函数在成形滤波器设计中的应用

讨论了具有奇对称过渡带的成形滤波器的设计问题，得到一个较为一般性的结论：在频域上，成形滤波函数为一个理想低通滤波函数与一个窗函数的卷积；其中升余弦滚降滤波器为一特例。在理论上进一步证明了引入滚降系数可以降低对采样时钟精度的要求。理论分析和数值分析的结果表明升余弦滚降滤波器并非一较好的滤波器。     

基于MATLAB的数字基带传输的FIR滤波器的设计

为了消除数字基带传输系统中的码间串扰,可将FIR数字滤波器应用于消除码间串扰的升余弦滚降特性低通滤波器的设计中。文中简要介绍了FIR数字滤波器的特征,给出了运用MATLAB实现FIR数字滤渡器的设计与仿真方法．同时给出了将设计结果应用于消除码间串扰的数字基带传输系统中操作过程。     

基于FPGA的高阶高速FIR滤波器设计与实现

提出了一种基于FPGA的高阶高速FIR滤波器的设计与实现方法。通过一个169阶的均方根升余弦滚降滤波器的设计，介绍了如何应用流水线技术来设计高阶高速FIR滤波器，并且对所设计的FIR滤波器性能、资源占用进行了分析。     

基于FPGA的高阶高速FIR滤波器设计与实现

提出了一种基于FPGA的高阶高速FIR滤波器的设计与实现方法。通过一个169阶的均方根升余弦滚降滤波器的设计,介绍了如何应用流水线技术来设计高阶高速FIR滤波器,并且对所设计的FIR滤波器性能、资源占用进行了分析。     

基于FPGA的高阶高速FIR滤波器设计与实现

提出了一种基于FPGA的高阶高速FIR滤波器的设计与实现方法.通过一个169阶的均方根升余弦滚降滤波器的设计,介绍了如何应用流水线技术来设计高阶高速FIR滤波器,并且对所设计的FIR滤波器性能、资源占用进行了分析.     

基于FPGA的SRRC数字滤波器设计与实现

随着数字技术的不断发展,数字滤波在数字信号处理领域占据不可替代的地位。文章首先介绍了数字滤波器的理论,DSP器件在高速和实时系统中的应用有一定局限性的问题提出了基于FPGA消除基带传输系统码间干扰的实现方案。该方案设计了一个33阶的具有对称转置结构的平方根升余弦滚降(SRRC)滤波器。首先通过MATLAB对滤波器系数进行了提取,并对浮点型系数进行量化和CSD编码形成定点型系数,使之能够在FPGA中运行。利用硬件描述语言Verilog对所设计的滤波器各功能模块进行设计。最后釆用仿真综合软件Modelsim和Quartus II对顶层模块进行综合与仿真。仿真后得到的滤波后数据波形图与Matlab下理论性的滤波后数据波形图基本相吻合,证明了所设计的SRRC数字滤波器功能完全正确。     

基于FPGA的FIR升余弦滚降滤波器设计与实现

为了降低FIR滤波器对FPGA资源的消耗,同时能够直接验证其滤波性能。文中采用乘法器和加法器共享以及MEALY型状态机的实现方法,以及卷积、插零等算法,来实现FIR升余弦滚降滤波设计,同时给出了在Quartus II环境下的时序仿真结果。实践表明,此方法可以节省大量的FPGA资源,仅仅需要100多个LE逻辑单元,就可以有效解决FIR数字滤波器算法在FPGA设计中资源紧张的问题。     

基于非递归结构的多级余弦CIC滤波器

由于CIC抽取滤波器的实现无需使用乘法器与存储器,而使其具有快速变换采样的特点且便于实现,在软件无线电中得到广泛应用。由于传统的CIC抽取滤波器的线性性较差,即带外抑制不够且带内失真严重。文中提出了基于级联的余弦滤波器以优化传统的CIC抽取滤波器性能,通过提升余弦滤波器的滚降对阻带的压制及多级变速来提高其效率与线性性,从而达到优化目的,并通过仿真证明了方法的有效性。     

Switching considerations to combat spectral pollution in TDMA forsatellite broadcasting

A better switching technique for combating spectral pollution i.e. spectral spreading of burst time-division multiple access (TDMA) digital FM and π/4-QPSK (quadrature phase-shift keying) systems, is proposed. The effects of rectangular, linear, and raised cosine ramp on/off switching are examined for two prototypes using both hardware experimental methods and computer simulation for different gating rates, duty cycles, roll-off factors of transmitter filter and ramp on/off times. The measures results agree with the computer simulation results and indicate that the adjacent channel interference (ACI) caused by the burst operating in TDMA π/4-QPSK is significantly reduced by raised cosine switching in comparison with other types of switching     

无线电台中DS/D-MPSK调制解调器的FPGA实现

提出了一种通用数字DS/D-MPSK调制和解扩解调器的实现方案。该方案采用了成型滤波、直接数字合成(DDS)、正交调制、数字匹配滤波和延时差分解调等技术,直接在中频上进行数字信号处理,不需要进行数字下变频,也不需要进行伪随机码同步捕获和载波提取,简单易行,具有一定的新意和较高的实用价值。本方案已经应用于某军用超短波电台中,验证了方案的正确性和可行性。     

PAPR Reduction in Single Carrier FDMA Uplink by Pulse Shaping Using a β-α Filter

A novel pulse shaping filter satisfying the Nyquist-I criterion was derived and implemented to reduce the peak-to-average power ratio (PAPR) over a Single Carrier Frequency Division Multiple Access (SC-FDMA) scheme. The new filter reduces the PAPR, while maintaining the same excess bandwidth and the zero intersymbol interference condition. The novel filter contains a new design parameter β to minimize PAPR, which is independent from the roll-off factor α. The minimum PAPR of the SC-FDMA scheme is linked to the value given to the parameter β for a specific roll-off factor α. Several simulations showed that PAPR is reduced greatly compared to that of the raised cosine filter, which is widely used in wireless communications. The performance of the proposed pulse shaping filter, regarding PAPR, is also compared with those of other conventional filters, demonstrating that the new filter has a superior performance.     

Mixed-signal matched filter for high-rate communication systems

A mixed-signal programmable filter suitable for high-rate communication systems is addressed. The proposed filter has analogue input and analogue-sampled outputs. The filter taps are stored in a digital memory and can be changed on the fly which is desirable in many practical applications such as adaptive filtering. The filter structure is based on a bank of digitally controlled transconductors along with small capacitors. The employed transconductors are based on simple Complementary Metal-Oxide Semiconductor (CMOS) transistors and thus can be integrated efficiently with the digital parts of systems. A cosine roll-off filter is designed and investigated by simulation in time and frequency domains. The results show that the proposed structure has a good speed-complexity-consumption trade-off.     

基于FPGA实现根升余弦滤波器的研究

本文研究了数字通信系统中发送端的根升余弦滚降滤波器的原理和多相结构,分析讨论了该滤波器基于分布式算法(DA)和CSD编码的FPGA设计,并用ALTERA公司的FP-GA芯片进行了验证,最后给出了结果比较和分析。本文对基于FPGA的无线通信modem的设计有重要意义。     

Design of interpolation filter for all digital receiver—On the interpolation problem of full response modulation signals

All digital implementation of receiver is a main topic on digital communication recently. The design of interpolation filter is one of the important problems for all digital implementation of receiver. In this paper, for full response linear modulation signal, a interpolation criterion is proposed. An interpolation formula is presented on bandwidth-limited transmission signal. For example, using the raised cosine roll off function as the system pulse response, the feasibility and effectiveness on the interpolation formula are certified by theoretical and numerical analysis. The computer simulation result on 16-QAM signal is given.