Ni-Cr合金钎料激光钎焊金刚石表面金属化

为了研究激光钎焊金刚石磨粒表面金属化生成物类别与形成机制, 采用第一性原理的密度泛函理论对常见碳化物进行了计算, 并采用Ni-Cr合金钎料, 借助光纤激光热源对金刚石磨粒进行了激光钎焊试验, 获得了Cr₃C₂和Cr₇C₃两种碳化物的结构和力学性能参量以及金刚石磨粒表面微结构和碳化物种类。结果表明, Cr₃C₂和Cr₇C₃两者都具有金属性, 且后者韧性更强; 激光钎焊得到的金刚石磨粒与Ni-Cr合金钎料界面冶金反应层厚度约为4μm, 金刚石磨粒表面碳化物主要为Cr₃C₂; 超声辅助激光钎焊得到的金刚石磨粒表面碳化物为Cr₃C₂和Cr₇C₃, 超声波高频振动可以促进界面反应, 进而生成含碳量低的Cr₇C₃。此研究结果对激光钎焊金刚石技术的发展具有指导意义。     

钝化处理对Al2O3/InP MOS电容界面特性的影响

制备了Al/Al_2O_3/InP金属氧化物半导体(MOS)电容,分别采用氮等离子体钝化工艺和硫钝化工艺处理InP表面。研究了在150、200和300 K温度下样品的界面特性和漏电特性。实验结果表明,硫钝化工艺能够有效地降低快界面态,在150 K下测试得到最小界面态密度为1.6×10¹⁰ cm^-2·eV^-1。与硫钝化工艺对比,随测试温度升高,氮等离子体钝化工艺可以有效减少边界陷阱,边界陷阱密度从1.1×10¹² cm^-2·V^-1降低至5.9×10¹¹ cm^-2·V^-1,同时减少了陷阱辅助隧穿电流。氮等离子体钝化工艺和硫钝化工艺分别在降低边界陷阱和快界面态方面有一定优势,为改善器件界面的可靠性提供了依据。     

界面对封装用金刚石/铝复合材料性能的影响

通过对表面改性后的金刚石同铝粉进行烧结,对比研究了不同的界面层对复合材料导热率的影响。实验表明,通过表面改性制备的镀Ti金刚石/Al复合材料,在同样制备条件下其热导率和致密度性能优于表面未镀覆的金刚石/Al复合材料。金属基体中,Si元素的添加能有效降低烧结体的烧结温度,但是其热导率低于基体中未添加杂质元素的镀Ti金刚石/Al复合材料。金刚石/Al复合材料的热导率同界面结构有关,镀覆合适的金属元素能有效改善金刚石对铝的润湿性,降低界面热阻,从而能有效提高金刚石/铝复合材料的导热率。     

金刚石/银复合材料:制备、电泳沉积及场发射性能研究

采用化学镀银的方法,制备了银包覆的金刚石复合材料,并利用场发射扫描电子显微镜(FESEM)、X射线衍射仪(XRD)和拉曼(Raman)光谱对样品的形貌和微结构进行了表征。利用电泳沉积的方法,制备了均匀的金刚石/银复合材料薄膜,场发射测试结果表明,在22 V/μm的电场下,金刚石/银复合材料的发射电流密度可达23.7μA/cm2;而在26 V/μm的电场下,高压金刚石薄膜的发射电流密度仅为0.2μA/cm2。与高压金刚石薄膜的场发射结果相比,金刚石/银复合材料的场发射性能有明显的提高。银的存在使银与金刚石界面处形成电子发射区,在外加电场作用下,该区域电子优先隧穿表面势垒逸出到真空,形成场致电子发射。     

Li2CO3掺杂BST的制备及复合薄片的能量收集研究

将水基流延技术与低温烧结陶瓷技术相结合,用于BST挠曲电陶瓷的研制和能量的收集。为了降低BST的烧结温度,在BST水基流延浆料中添加了质量分数1%～4%的Li₂CO₃,将浆料流延成薄片后进行烧结。研究了Li₂CO₃掺杂量对烧结温度的影响以及BST薄片厚度对材料电性能的影响。实验结果表明,适量的Li₂CO₃掺杂能够将BST的烧结温度降低约250℃。在烧结后的薄片两面涂上银电极和适当厚度的PDMS,得到“三明治结构”的BST复合薄片,用于介电、挠曲电测试和能量收集实验。当Li₂CO₃掺杂量为质量分数2%时,300μm厚的BST复合薄片在1100℃烧结后介电性能最优,其介电常数为3200,介质损耗为0.05。而200μm厚的复合薄片表现出最高的横向挠曲电系数,达到0.24μC/m。此外,40μm厚的复合薄片表现出最好的电流输出能力,达到1.2 nA。     

石墨转化纳米金刚石相变分子动力学模拟研究

为了探讨1维微尺度热传导模型不同激光能量对石墨转化纳米金刚石相变机理的影响，采用基于密度泛函理论的分子动力学方法模拟优化后的石墨结构，用有限差分法计算了激光辐照石墨表面的温度分布；基于sp³杂化键可以明显地区分金刚石和石墨结构，根据能量耦合得到不同激光能量条件下辐照石墨的态密度带隙，研究了碳原子键合条件。结果表明，只有当激光能量达到5 J时，才能形成少量sp³杂化碳原子；随着激光能量的增加，液相下受辐照的石墨表面的温度随之增加，碳原子中的自由电子更容易移动到成键分子轨道，电子的电负性增强，从而增强sp³键的极性，并有助于将sp²键转变为sp³键。该研究结果对在液相激光辐照下提升纳米金刚石制备效率、探究纳米金刚石制备机理有重要的现实意义。     

银纳米材料的纳连接及其电学性能研究

随着微电子器件需求日益迫切,由纳米材料构造的微纳结构在降低尺度并获得特征性能上有着极大的优势。纳连接是从纳米材料构筑微纳结构的有效途径,目前实现纳连接的手段主要包括热烧结、激光烧结等。对比研究了不同连接方法形成的银电极的电学性能及微观结构,并对银纳米材料间的连接机理进行了分析。结果表明,相比于自连接及热烧结,激光烧结在降低电阻率及保持纳米结构方面有着独特的优势,在激光诱导下,银纳米带可在低温下实现互连,形成交联网络结构,从而降低银电极的电阻率,并显著改善其柔韧性。激光烧结电极的电阻率低至1.88×10~(-7)Ω·m,同时具有较好连接强度,经3000次弯折后电阻变化率仅为21.26%。     

基于反相微乳液体系制备低温烧结纳米银浆的工艺方法

采用span80-Triton X-100/正己醇/正庚烷/水相四元反相微乳液体系制备低温烧结纳米银浆,研究了span80与Triton X-100形成的复配表面活性剂对反相微乳液体系稳定性的影响,并分析成分含量对该体系增溶水量的影响。结果表明:span80与Triton X-100形成的复配表面活性剂表现出协同作用的特点;该复配表面活性剂最佳HLB值(亲水亲油平衡值)为10.63;且随着助表面活性剂正己醇含量的增加,体系增溶水量先增大后减小;最终得到银颗粒粒径约20 nm的低温烧结纳米银浆。     

高导热金刚石/玻璃复合材料的制备和性能研究

首先对金刚石颗粒进行化学镀Cu,并控制氧化,从而在金刚石颗粒表面获得Cu-Cu2O复合结构。然后,在800℃无压烧结制备了金刚石/玻璃复合材料,观察了其表面和界面形貌,并测定了其相对密度和热导率。结果表明,通过对镀Cu金刚石的控制氧化,明显改善了玻璃对金刚石颗粒表面的润湿性,避免了玻璃对金刚石颗粒表面的侵蚀,提高了复合材料的热导率;复合材料的热导率随金刚石含量的增加而增加,当金刚石质量分数为70%时,热导率最高达到了14.420W/(m·K)。     

YON界面钝化层改善HfO2/Ge界面特性的研究

本文采用YON界面钝化层来改善HfO₂栅介质Ge metal-oxide-semiconductor（MOS）器件的界面质量和电特性.比较研究了两种不同的YON制备方法：在Ar+N₂氛围中溅射Y₂O₃靶直接淀积获得以及先在Ar+N₂氛围中溅射Y靶淀积YN再于含氧氛围中退火形成YON.实验结果及XPS的分析表明,后者可以利用YN在退火过程中先于Ge表面吸收从界面扩散的O而氧化,从而阻挡了O扩散到达Ge表面,更有效抑制了界面处Ge氧化物的形成,获得了更优良的界面特性和电特性：较小的CET（1.66 nm）,较大的k值（18.8）,较低的界面态密度（7.79×10¹¹ eV^-1cm^-2）和等效氧化物电荷密度（-4.83×10¹² cm^-2）,低的栅极漏电流（3.40×10^-4 A/cm²@V_g=V_fb+1 V）以及好的高场应力可靠性.     

Thermal Boundary Resistance Between GaN and Substrate in AlGaN/GaN Electronic Devices

The influence of a thermal boundary resistance (TBR) on temperature distribution in ungated AlGaN/GaN field-effect devices was investigated using 3-D micro-Raman thermography. The temperature distribution in operating AlGaN/GaN devices on SiC, sapphire, and Si substrates was used to determine values for the TBR by comparing experimental results to finite-difference thermal simulations. While the measured TBR of about 3.3 x 10^-8 W^-1 ldr m² ldr K for devices on SiC and Si substrates has a sizeable effect on the self-heating in devices, the TBR of up to 1.2 x 10^-8 W^-1 ldr m² ldr K plays an insignificant role in devices on sapphire substrates due to the low thermal conductivity of the substrate. The determined effective TBR was found to increase with temperature at the GaN/SiC interface from 3.3 x 10^-8 W^-1 ldr m² ldr K at 150degC to 6.5 x 3.3 x 10^-8 W^-1 ldr m² ldr K at 275degC, respectively. The contribution of a low-thermal-conductivity GaN layer at the GaN/substrate interface toward the effective TBR in devices and its temperature dependence are also discussed.     

Interface characterization of silicon epitaxial lateral growth overexisting SiO2 for three-dimensional CMOS structures

The silicon-silicon dioxide interface created by the epitaxial lateral growth of monocrystalline silicon (ELO) over existing thermally oxidized silicon was investigated using a novel device structure. This structure is proposed as the basic building block of technology for the fabrication of locally restricted three-dimensional integrated CMOS circuits, as well as advanced bipolar devices. Results are reported from the investigation of the surface states of this silicon-on-insulator (SOI) interface. It is demonstrated that these interfaces can exhibit characteristics comparable to those interfaces created by the thermal oxidation of silicon. The SOI interface surface state densities, as grown, were measured to be about 2×10¹¹ cm^-2 eV^-1 at midgap energies. It is believed that H₂ from the epitaxial growth ambient is trapped at the interface and neutralizes surface states     

Electrical characterization of ultra-shallow junctions formed bydiffusion from a CoSi2 layer

Ultra-shallow p⁺/n and n⁺/p junctions were fabricated using a Silicide-As-Diffusion-Source (SADS) process and a low thermal budget (800-900°C). A thin layer (50 nm) of CoSi₂ was implanted with As or with BF₂ and subsequently annealed at different temperatures and times to form two ultra-shallow junctions with a distance between the silicide/silicon interface and the junction of 14 and 20 nm, respectively. These diodes were investigated by I-V and C-V measurements in the range of temperature between 80 and 500 K. The reverse leakage currents for the SADS diodes were as low as 9×10 ^-10 A/cm² for p⁺/n and 2.7×10^-9 A/cm² for n⁺/p, respectively. The temperature dependence of the reverse current in the p ⁺/n diode is characterized by a unique activation energy (1.1 eV) over all the investigated range, while in the n⁺/p diode an activation energy of about 0.42 eV is obtained at 330 K. The analysis of the forward characteristic of the diodes indicate that the p⁺ /n junctions have an ideal behavior, while the n⁺/p junctions have an ideality factor greater than one for all the temperature range of the measurements. TEM delineation results confirm that, in the case of As diffusion from CoSi₂, the junction depth is not uniform and in some regions a Schottky diode is observed in parallel to the n⁺/p junction. Finally, from the C-V measurements, an increase of the diodes area of about a factor two is measured, and it is associated with the silicide/silicon interface roughness     

MOSFET transistors fabricated with high permitivity TiO2dielectrics

Layers of polycrystalline anatase TiO₂ have been deposited through the thermal decomposition of titanium tetrakisisopropoxide (TTIP). 500 Å films deposited and annealed in oxygen at 750°C had average roughnesses (R_a) of about 30 Å. Capacitors made from 190 Å layers of TiO₂ displayed a voltage dependent accumulation capacitance. This was postulated to be caused by finite width effects in the accumulation layer which we have dubbed the quantum capacitance effect. N-channel transistors made with these films showed near ideal behavior, but mobilities were significantly lower than those of thermal oxide MOSFETs. This mobility reduction was believed to be caused by interface states, which fell below 10¹¹ cm^-2 eV^-1 at midgap, but rose sharply on either side, unlike the “U” shaped behavior in thermal oxide MOSFET's     

Thin-gate oxides prepared by pure water anodization followed byrapid thermal densification

Anodic oxidation at room temperature with pure deionized water as electrolyte and then followed by high-temperature rapid thermal densification was used to prepare high breakdown endurance thin-gate oxides with thicknesses of about 50 Å. It was observed that the oxides prepared by anodic oxidation followed by rapid thermal densification (AOD) show better electrical characteristics than those grown by rapid thermal oxidation (RTO) only. The AOD oxides have a very low midgap interface trap density, Ditm, of smaller than 1×10¹⁰ eV^-1 cm^-2 and negative effective oxide trapped charge. From the smaller leakage currents observed during staircase ramp voltage time-zero dielectric breakdown (TZDB) and constant field time-dependent dielectric breakdown (TDDB) testings, it is supposed that the uniform interfacial property and the pretrapped negative charges in AOD oxides are responsible for the improved characteristics     

Nitrogen Implantation to Improve Electron Channel Mobility in 4H-SiC MOSFET

Normally off 4H-SiC MOSFET devices have been fabricated on a p-type semiconductor and electrically characterized at different temperatures. A gate oxide obtained by nitrogen ion implantation performed before the thermal oxidation of SiC has been implemented in n-channel MOSFET technology. Two samples with a nitrogen concentration at the SiO₂/SiC interface of 5 X 10¹⁸ and 1.5 X 10¹⁹ cm^-3 and one unimplanted sample have been manufactured. The sample with the highest N concentration at the interface presents the highest channel mobility and the lowest threshold voltage. For increasing temperature, in all the samples, the threshold voltage decreases, and the electron channel mobility increases. The latter case attains a maximum value of about 40 cm²/V ldr s at 200degC for the sample with the highest N concentration. These trends are explained by the reduction of interface electron traps in the upper half of the band gap toward the conduction band edge. These results demonstrate that N implantation can be effectively used to improve the electrical performances of an n-type surface channel 4H-SiC MOSFET.     

Influence of Ag+-Na+ ion-exchange equilibriumon waveguide index profiles

The Ag⁺-Na⁺ ion-exchange process in a soda-lime silicate glass was studied at 330° as a function of composition of AgNO₃-NaNO₃ melt, mixing condition, and exchange time. The concentration profile of silver in glass was measured by atomic absorption spectroscopy and SEM technique. The surface index change and the index profile were determined from mode index measurement. Ion-exchange was modeled by an ion-diffusion limited process in the glass with an equilibrium chemical reaction at the melt-glass interface. A large value of 75 for the equilibrium constant at low-silver melt concentrations (<10^-2 mole fractions) shows that uptake of silver in glass varies in highly nonlinear fashion with the melt concentration. The results provide boundary conditions necessary for solution of the diffusion equation and design of single-mode waveguides     

Novel methods to incorporate deuterium in the MOS structures

The deuterium concentration as high as 2×10²⁰ cm ^-3 can be incorporated in rapid thermal oxide layers by a process of deuterium prebake and deuterium post oxidation anneal. The deuterium distributed not only at Si/oxide interface but also in the bulk oxide. The deuterium incorporation shows the improvement on soft breakdown characteristics and the interface state density at SiO₂ /Si after stress. The addition of very high vacuum prebake process yields a deuterium concentration of 9× 10²⁰ cm^-3 , but also leads to the formation of rough oxide     

An improvement of the interface properties of plasma anodized SiO2/Si system for the fabrication of MOSFET's

A new annealing process in chlorine ambient produced by passing argon through a CCl4container for reducing the interface states of the plasma anodized SiO2/Si system was developed. At optimum annealing conditions, the interface state density was reduced to about 1010states/eV . cm². Application of the oxide to the fabrication of MOSFET's shows that the devices obtained have lower threshold voltage and higher mobility than those fabricated with thermal oxidation in dry oxygen.     

Silicon nano-particles in SiO2 sol–gel film for nano-crystal memory device applications

A novel 2-bit nano-silicon based non-volatile memory is proposed to double memory density. The thin film structure exhibits two conduction states (ON and OFF) at different voltages and has a cost-effective structure. The structure utilizes the good electrical properties of fluorinated SiO₂ thin films, together with the bi-stable properties conferred by the nano-silicon particles therein embedded. A polymeric layer of 8-hydroxyquinoline aluminum salt (Alq3) further deposited on the top of the nano-particle layer through chemical evaporation and a silver paste contact determines the final structure. The positive 0–15 V scan reveals two discontinuities with an ON/OFF ratio of 10⁴–10⁵ (2–4 V) and OFF/ON of 10³ (12.5–13.0 V). The reverse scan displays again two distinct thresholds, range of 10.5–11.0 V (ON/OFF ratio 10⁻³), respectively, 0.5 V (OFF/ON ratio 10⁻⁵–10⁻⁴).