一种改进的Reed译码算法

Ｒｅｅｄ算法是一种大数逻辑译码算法,它最初用于Ｒｅｅｄ－Ｍｕｌｌｅｒ码,对很多大数逻辑可译码都是很有意义的。本文首先对Ｒｅｅｄ－Ｍｕｌｌｅｒ码的编码原理及Ｒｅｅｄ译码算法进行分析,然后根据其编码原理,提出对Ｒｅｅｄ算法中校验和产生方法的一种改进方案,最后对改进算法的有效性进行了分析。     

IEEE802.16e标准下LDPC码译码性能分析

LDPC码是一种逼近香农极限的线性分组码。对IEEE802.16e标准下LDPC码校验矩阵的构造及硬判决算法、BP算法、Log-BP算法和Min-Sum算法原理进行了简单介绍。基于Matlab仿真对不同码长译码性能及不同方法译码性能进行分析比较,结果显示随着码长的增加LDPC译码性能变好,讨论的几种译码算法中硬判决译码性能较差,Min-Sum译码好于硬判决译码,但稍差于BP译码和Log-BP译码,BP译码和Log-BP译码性能较好且基本一致。     

一种改进的LDPC码译码算法

文中提出了一种改进的基于加权错误校验的LDPC码比特反转算法,该算法不需要软信息,译码时采用了设定判决门限的方法,减少了译码过程中的迭代次数和译码复杂度.仿真结果表明:对于高Girth、低码率的LDPC码,该算法达到了比多种利用软信息的比特反转算法更少的迭代次数和更优异的性能.     

LDPC编译码算法分析

低密度奇偶校验(LDPC)码是一种线性分组码,其纠错能力可以接近香农极限。针对LDPC码的编译码问题,分析了校验矩阵的构造方法。给出了LDPC码的编码算法以及算法的实现结构。分析了基于软判决的置信传播(BP)译码算法,并给出了可以进一步降低计算复杂度的简化译码方法。通过仿真对比了不同的译码算法在高斯信道下的译码性能。     

量子稳定子码的概率译码

为了提高量子稳定子码的译码速率,提出了一种基于校验矩阵的量子概率译码算法。通过选择具有最小量子权重的算子作为差错算子来减少译码出错概率,通过预先构造量子标准阵列来缩短译码时间。与已有的量子最大似然译码算法相比,该算法对简并码和非简并码采用统一的译码方式,从而提高了简并码的译码可靠性。此外,算法不需要预先寻找差错算子对应的向量空间的基,因此算法复杂度更小。     

LDPC码全并行译码器的设计与实现

本论文用可编程逻辑器件(FPGA)实现了一种低密度奇偶校验码(LDPC)的编译码算法.采用基于Q矩阵LDPC码构造方法,设计了具有线性复杂度的编码器. 基于软判决译码规则,采用全并行译码结构实现了码率为1/2、码长为40比特的准规则LDPC码译码器,并且通过了仿真测试.该译码器复杂度与码长成线性关系,与Turbo码相比更易于硬件实现,并能达到更高的传输速率.     

空间耦合LDPC码的分层译码算法

针对长码长空间耦合低密度奇偶校验(SC-LDPC)码译码时延较长的问题,该文提出了分层滑动窗译码(LSWD)算法。该算法利用SC-LDPC子码码块的准循环特性和滑动窗内校验矩阵的层次结构,通过在滑动窗内对校验矩阵进行分层处理,优化层与层之间消息传递,从而加快窗内译码的收敛速度,减少了译码迭代次数。仿真和分析结果表明:在相同的信噪比(SNR)条件和相同的误码性能要求下,LSWD算法所需的迭代次数少于滑动窗译码(SWD)算法,特别在高信噪比下,LSWD算法的迭代次数约为SWD算法的一半,从而有效缩短全局译码时延;在相同译码迭代次数下,LSWD算法的译码性能优于SWD算法,而其计算复杂度增加不大。     

DVB-S2标准IRA-LDPC译码算法研究与改进

首先对DVB-S2标准LDPC码编码原理、IRA码以及校验矩阵的特征进行了分析,接着对该标准中LDPC码的Tanner图参数进行了总结,然后对不同的译码算法从性能和复杂度方面进行了比较,并且对不同迭代次数时LDPC码的判决信息的分布进行了分析,最后对各种译码算法的性能和复杂度进行了总结.仿真结果表明,SPA译码算法性能最优但是复杂度最大,MinSum算法的复杂度最低但是性能最差,而改进的MinSum算法则在复杂度和性能方面是前面两种算法的折中,对实际工程的应用有较强的借鉴作用.     

Reed-Muller码的大数逻辑译码及其与Viterbi算法的比较

文章首先介绍了Reed-Muller码的发展历史,以及构造其生成矩阵的特殊方法,从而对Reed-Muller进行编码。其次,重点讨论了Reed-Muller码的大数逻辑译码,这是一种适用于Reed-Muller码的简单又有效的译码方法,并举例进行了详细地阐述。Viterbi算法广泛应用于分组码、卷积码的译码,考虑到它的最优译码特性,文章运用Viterbi算法对ReedMuller码进行译码,将其性能与大数逻辑译码进行比较。由于Reed-Muller码的网格图比较复杂,文章提出一种方法,通过将线性分组码的生成矩阵转换成面向网格的形式,减少了网格图的状态数,从而降低了Viterbi译码的复杂性。     

基于校验子的Turbo乘积码仿真研究

针对Turbo乘积码译码延时的问题,提出一种基于校验子的Turbo乘积码译码算法(S-TPC),该算法根据校验子的值采取不同方式对每行(列)进行译码,节省了一部分校验子为0的码字的硬判决译码运算量。仿真结果表明,S-TPC(32,26)在迭代4次时,能在不降低译码性能的情况下,减少近50%的计算量。     

Application of circulant matrices to the construction and decodingof linear codes

The Fourier transform technique is used to analyze and construct several families of double-circulant codes. The minimum distance of the resulting codes is lower-bounded by 2√r and can be decoded easily employing the standard BCH decoding algorithm or the majority-logic decoder of Reed-Muller codes. A decoding procedure for Reed-Solomon codes is presented, based on a representation of the parity-check matrix by circulant blocks. The decoding procedure inherits both the (relatively low) time complexity of the Berlekamp-Massey algorithm and the hardware simplicity characteristic of Blahut's algorithm. The procedure makes use of the encoding circuit together with a reduced version of Blahut's decoder     

On the construction of a class of majority-logic decodable codes

The attractiveness of majority-logic decoding is its simple implementation. Several classes of majority-logic decodable block codes have been discovered for the past two decades. In this paper, a method of constructing a new class of majority-logic decodable block codes is presented. Each code in this class is formed by combining majority-logic decodable codes of shorter lengths. A procedure for orthogonalizing codes of this class is formulated. For each code, a lower bound on the number of correctable errors with majority-logic decoding is obtained. An upper bound on the number of orthogonalization steps for decoding each code is derived. Several majority-logic decodable codes that have more information digits than the Reed-Muller codes of the same length and the same minimum distance are found. Some results presented in this paper are extensions of the results of Lin and Weldon [11] and Gore [12] on the majority-logic decoding of direct product codes.     

LDPC码加权位翻转解码算法的研究

本文以Tanner图上的迭代消息流传递技术为基础,分析了Gallager提出的LDPC码第一解码方案,给出基于校验和的位翻转硬判决解码算法。在此基础上引入接收信号作为可靠性评估,使评估值作为硬判决的加权系数,从而提出基于校验和的加权位翻转解码算法。加权位翻转算法充分考虑了接收符号的信息;为了快速搜索翻转位,对不满足的校验方程数采用最大投票数排队算法。这些措施的合理应用改善了基于校验和的位翻转解码算法的性能。     

误码条件下LDPC码参数的盲估计

针对非合作信号处理中LDPC码（Low-Density Parity-Check）的盲识别问题,提出了一种容错能力较强的开集识别算法.该算法通过对码字矩阵进行高斯约旦消元找到汉明重量较小的"相关列",并根据"相关列"中所包含的约束关系求得LDPC码的校验向量,然后剔除"相关列"中为"1"位置对应的错误码字.若根据高斯约旦消元求校验向量和剔除错误码字进行迭代无法得到更多校验向量,则对得到的这些校验向量进行稀疏化,再进行译码纠错.最后,综合利用校验向量的求解,错误码字的剔除,校验向量稀疏化,LDPC码译码进行迭代,实现LDPC码校验矩阵的有效重建.仿真结果表明,对于IEEE 802.16e标准中的（576,288）LDPC码,在误比特率为0.0022时,本文算法仍可以达到较好的识别效果.     

Shortened finite geometry codes (Corresp.)

A method of shortening finite analytic geometry codes, projective-geometry (PG) codes, Euclidean-geometry (EG) codes, and 2-fold EG codes is presented. The shortened codes preserve the feature of being majority-logic decodable and they have the same error-correcting capability as the original codes. Combinatorial expressions for the parity-check symbols of the shortened codes are derived.     

Error-erasure decoding of product codes (Corresp.)

Two error-erasure decoding algorithms for product codes that correct all the error-erasure patterns guaranteed correctable by the minimum Hamming distance of the product code are given. The first algorithm works when at least one of the component codes is majority-logic decodable. The second algorithm works for any product code. Both algorithms use the decoders of the component codes.     

On majority-logic decoding for duals of primitive polynomial codes

The class of polynomial codes introduced by Kasami et al. has considerable inherent algebraic and geometric structure. It has been shown that this class of codes and their dual codes contain many important classes of cyclic codes as subclasses, such as BCH codes, Reed-Solomon codes, generalized Reed-Muller codes, projective geometry codes, and Euclidean geometry codes. The purpose of this paper is to investigate further properties of polynomial codes and their duals. First, majority-logic decoding for the duals of certain primitive polynomial codes is considered. Two methods of forming nonorthogonal parity-check sums are presented. Second, the maximality of Euclidean geometry codes is proved. The roots of the generator polynomial of an Euclidean geometry code are specified.     

Distributed decoding of cyclic block codes using a generalizationof majority-logic decoding

One-step majority-logic decoding is one of the simplest algorithms for decoding cyclic block codes. However, it is an effective decoding scheme for very few codes. This paper presents a generalization based on the “common-symbol decoding problem.” Suppose one is given M (possibly corrupted) codewords from M (possibly different) codes over the same field; suppose further that the codewords share a single symbol in common. The common-symbol decoding problem is that of estimating the symbol in the common position. This is equivalent to one-step majority logic decoding when each of the “constituent” codes is a simple parity check. This paper formulates conditions under which this decoding is possible and presents a simple algorithm that accomplishes the same. When applied to decoding cyclic block codes, this technique yields a decoder structure ideal for parallel implementation. Furthermore, this approach frequently results in a decoder capable of correcting more errors than one-step majority-logic decoding. To demonstrate the simplicity of the resulting decoders, an example is presented     

High-Rate Nonbinary Regular Quasi-Cyclic LDPC Codes for Optical Communications

The parity-check matrix of a nonbinary (NB) low-density parity-check (LDPC) code over Galois field GF(q) is constructed by assigning nonzero elements from GF(q) to the 1s in corresponding binary LDPC code. In this paper, we state and prove a theorem that establishes a necessary and sufficient condition that an NB matrix over GF(q), constructed by assigning nonzero elements from GF(q) to the 1s in the parity-check matrix of a binary quasi-cyclic (QC) LDPC code, must satisfy in order for its null-space to define a nonbinary QC-LDPC (NB-QC-LDPC) code. We also provide a general scheme for constructing NB-QC-LDPC codes along with some other code construction schemes targeting different goals, e.g., a scheme that can be used to construct codes for which the fast-Fourier-transform-based decoding algorithm does not contain any intermediary permutation blocks between bit node processing and check node processing steps. Via Monte Carlo simulations, we demonstrate that NB-QC-LDPC codes can achieve a net effective coding gain of 10.8 dB at an output bit error rate of 10^-12. Due to their structural properties that can be exploited during encoding/decoding and impressive error rate performance, NB-QC-LDPC codes are strong candidates for application in optical communications.     

One-step majority-logic decoding with symbol reliability information (Corresp.)

A method of using reliability information in one-step majority-logic decoders is presented. The idea is, basically, that the received binary digits are corrected in an order such that the least reliable digit is first corrected. With this method the error correction capability of the decoder is extended for large signal-to-noise ratios (SNR's). Different decoding algorithms are used when the number of orthogonal parity-check sums are even and odd, respectively. Computer simulations are presented for some short codes with binary antipodal signals on the additive white Gaussian noise channel.