An efficient current-based logic cell model for crosstalk delay analysis

Logic cell modelling is an important component in the analysis and design of CMOS integrated circuits, mostly due to nonlinear behaviour of CMOS cells with respect to the voltage signal at their input and output pins. A current-based model for CMOS logic cells is presented, which can be used for effective crosstalk noise and delta delay analysis in CMOS VLSI circuits. Existing current source models are expensive and need a new set of Spice-based characterisation, which is not compatible with typical EDA tools. In this article we present Imodel, a simple nonlinear logic cell model that can be derived from the typical cell libraries such as NLDM, with accuracy much higher than NLDM-based cell delay models. In fact, our experiments show an average error of 3% compared to Spice. This level of accuracy comes with a maximum runtime penalty of 19% compared to NLDM-based cell delay models on medium-sized industrial designs.     

Variable Input Delay CMOS Logic for Low Power Design

We propose a new complementary metal-oxide semiconductor (CMOS) gate design that has different delays along various input to output paths within the gate. The delays are accomplished by inserting selectively sized ldquopermanently onrdquo series transistors at the inputs of a logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementations of digital circuits. Applying a linear programming method to the c7552 benchmark circuit and using the gates described in this paper, we obtained a power saving of 58% over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. The optimized circuits had the same critical path delays as their original unoptimized versions. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on noncritical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers.     

The Effect of Signal Activity on Propagation Delay of CMOS Logic Gates Driving Coupled On-Chip Interconnections

The effect of interconnect coupling capacitances on neighboring CMOS logic gates driving coupled interconnections strongly depends upon signal activity. A transient analysis of two capacitively coupled CMOS logic gates is presented in this paper for different combinations of signal activity. The uncertainty of the effective load capacitance and propagation delay due to signal activity is addressed. Analytical expressions characterizing the output voltage and propagation delay are also presented for different signal activity conditions. The propagation delay based on these analytical expressions is within 3% as compared to SPICE, while the estimated delay neglecting the difference between the load capacitances can exceed 45%. The logic gates should be properly sized to balance the load capacitances in order to minimize any uncertainty in the delay and load. The peak noise voltage on a quiet interconnection determined from the analytical expressions is within 4% of SPICE. The peak noise voltage on a quiet interconnection can be minimized if the effective output conductance of the quiet logic gate driving the interconnect is increased.     

Pass transistor with dual threshold voltage domino logic design using standby switch for reduced subthreshold leakage current

Dual threshold voltages domino design methodology utilizes low threshold voltages for all transistors that can switch during the evaluate mode and utilizes high threshold voltages for all transistors that can switch during the precharge modes. We employed standby switch can strongly turn off all of the high threshold voltage transistors which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current. Subthreshold leakage currents are especially important in burst mode type integrated circuits where the majority of the time for system is in an idle mode. The standby switch allowed a domino system enters and leaves a low leakage standby mode within a single clock cycle. In addition, we combined domino dynamic circuits style with pass transistor XNOR and CMOS NAND gates to realize logic 1 output during its precharge phase, but not affects circuits operation in its evaluation and standby phase. The first stage NAND gates output logic 1 can guarantee the second stage computation its correct logic function when system is in a cascaded operation mode. The processing required for dual threshold voltage circuit configuration is to provide an extra threshold voltage involves only an additional implant processing step, but performs lower dynamic power consumption, lower delay and high fan-out, high switching frequencies circuits characteristics. SPICE simulation for our proposed circuits were made using a 0.18 µm CMOS process from TSMC, with 10 fF capacitive loads in all output nodes, using the parameters for typical process corner at 25 °C, the simulation results demonstrated that our designed 8-bit carry look-ahead adders reduced chip area, power consumption and propagation delay time more than 40%, 45% and around 20%, respectively. Wafer based our design were fabricated and measured, the measured data were listed and compared with simulation data and prior works. SPICE simulation also manifested lower sensitivity of our design to power supply, temperature, capacitive load and process variations than the dynamic CMOS technologies.     

A comprehensive delay model for CMOS inverters

A method to accurately calculate the delay and the output transition-time of a CMOS inverter for any input ramp and output loading is considered. This paper is an extension of Sakurai's work (1990) on delay modeling of inverters for fast input ramps. We observed that two different mechanisms, that can be adequately modeled analytically, govern the delay and the output transition-time of an inverter in two extreme cases: infinitely fast and infinitely slow inputs. These extreme points are joined by a curve that can predict the delay and the output transition-time for any input. We found that the delay and the output transition-time for an inverter with small fanouts are similar to those for large input transition-times. This behavior is explained by the use of I-V trajectories. We describe a method to generate parameters to model delay and output transition-time for different fanouts and input transition-times; this method can be generalized to add parameters for different temperatures and supply voltages. Given a new process technology and its corresponding SPICE-model parameters, our delay calculation scheme comprises characterizing a minimal number of coefficients for each new technology (a one-time process) and evaluating the analytical forms thereafter to obtain the delay and the transition-time. Our delay equations also explain negative delays that arise in case of slow input rise-times. A program incorporating the above idea has been implemented in C. Delay and transition-time values obtained from the program have been found to be typically within 3% of SPICE     

CMOS current steering logic for low-voltage mixed-signal integratedcircuits

A quiet logic family-complementary metal-oxide-semiconductor (CMOS) current steering logic (CSL)-has been developed for use in low-voltage mixed-signal integrated circuits. Compared to a CMOS static logic gate with its output range of ΔV_logic≈V_dd , a CSL gate swings only ΔV_logic≈V_T+0.25 V because the constant current supplied by the PMOS load device is steered to ground through either an NMOS diode-connected device or switching network. Owing to the constant current, digital switching noise is 100× smaller than in static logic. Another useful feature which can be used to calibrate CSL speed against process, temperature, and voltage variations is propagation delay that is approximately constant versus supply voltage and linear with bias current. Several CSL circuits have been fabricated using 0.8 and 1.2 μm high-V_T n-well CMOS processes. Two self-loaded 39-stage ring oscillators fabricated using the 1.2 μm process (1.2 V power supply) exhibited power-delay products of 12 and 70 fJ with average propagation delays of 0.4 and 0.7 ns, respectively. High-V_T and low-V_T CSL ALU's were operational at V _dd≈=0.70 V and V_dd≈0.40 V, respectively     

Design and realization of high-performance wave-pipelined 8×8b multiplier in CMOS technology

Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 μm technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well     

Hysteresis effect in floating-body partially depleted SOI CMOS domino circuits

This paper investigates in detail the basic mechanisms of hysteretic delay and noise margin variations for floating-body partially depleted SOI CMOS domino circuits. We first consider the ‘clock cycling scenario’, which completely eliminates (or isolates) the hysteresis effect of the output inverter, thus allowing one to observe and understand the hysteresis effect of the front-end domino logic stage. Three cases, based on whether the input signals are domino input signals, from other domino circuits, static input signals, from static circuits or latches; or a combination of domino and static input signals, are examined and differentiated. It is shown that hysteretic delay variation is the largest and the noise margin worst for the case with mixed domino and static input signals. Although the delay and noise margin disparities among the three types of input signals are significant at the beginning of the clock cycles, they converge as the circuit approaches steady state. The ‘data cycling scenario’ with the combined hysteresis effect of both the front-end domino logic stage and the output inverter is then discussed. Circuits operating under the ‘data cycling scenario’ are shown to have less body charge loss through the switching cycles than under the ‘clock cycling scenario’.     

变论域自适应模糊控制器的CMOS模拟 电路芯片实现

为解决传统的自适应模糊控制器算法过于复杂难以用模拟电路实现的问题,本文研究了输入输出论域可随输入变量的变化而自适应变化的在线自适应模糊控制器及其在非线性系统控制中的应用,并制作了CMOS模拟电路芯片.提出了一种新的尖三角形隶属度函数实现输入变论域的功能,输出变论域部分采用对输入变量进行加权积分并求其绝对值的方法.控制器的其他部分为求小电路和重心法去模糊电路.以上各电路均为CMOS模拟电路,它们和集成的整体电路均在无锡上华(CSMC) 0.6μm工艺下流片,测试结果表明该芯片完成了变论域模糊控制器的功能.     

一种新型低噪声电流控制逻辑的分析与设计

本文绘出了一种新型电流控制逻辑的电路结构和工作原理，并由此提出了该逻辑的优化设计方法。通过采用恒定工作电流和限制电路的输出逻辑摆幅，电流控制逻辑能避免静态CMOS电路工作时引入的瞬态开关噪声电流。理论分析和电路模拟结果都表明，和静态CMOS电路相比，电流控制逻辑的峰值开关电流下降了近两个数量级．该逻辑可应用在高性能的模／数混合集成电路中。     

Precomputation-based sequential logic optimization for low power

We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. We present two different precomputation architectures which exploit this observation. The primary optimization step is the synthesis of the precomputation logic, which computes the output values for a subset of input conditions. If the output values can be precomputed, the original logic circuit can be “turned off” in the next clock cycle and will have substantially reduced switching activity. The size of the precomputation logic determines the power dissipation reduction, area increase and delay increase relative to the original circuit. Given a logic-level sequential circuit, we present an automatic method of synthesizing precomputation logic so as to achieve maximal reductions in power dissipation. We present experimental results on various sequential circuits. Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay     

ATM交换中输入输出开窗排队算法的改进

本文为ＡＴＭ交换系统提出了一种改进的输入输出开窗算法，通过在原有输入开窗排队算法中引入因子Ｐｓ，改进算法允许至多Ｐｓ个信元同时到达同一输出口，并利用输入输出缓冲队列来减缓输出碰撞，改进的开窗算法不仅能得到几科与输出排队一亲的最优吞吐和延迟性能，还具有好得多的分组单元丢失性能，尤其适合缓冲容量有限的情形，因而不失为一有效的ＡＴＭ交换系统设计方案，本文讨论了算法及其复杂度分析，给出了计算机仿真的性能结     

High performance low power CMOS dynamic logic for arithmetic circuits

This paper presents the design of high performance and low power arithmetic circuits using a new CMOS dynamic logic family, and analyzes its sensitivity against technology parameters for practical applications. The proposed dynamic logic family allows for a partial evaluation in a computational block before its input signals are valid, and quickly performs a final evaluation as soon as the inputs arrive. The proposed dynamic logic family is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, circuits based on the proposed concept perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low power feature of the propose dynamic logic provides for smaller propagation time delay (3.5 times), lower energy consumption (55%), and similar combined delay, power consumption and active area product (only 8% higher), while exhibiting lower sensitivity to power supply, temperature, capacitive load and process variations than the dynamic domino CMOS technologies.     

CMOS delay time model based on weighted peak current

The authors propose a new CMOS delay time model with the configuration ratio, the input slope and the load condition taken into account. This model is based on the optimally weighted switching peak current. The delay equations are computationally effective and the error is typically within 10% of SPICE results     

A stuck fault model for dynamic CMOS combinational circuits

This paper utilizes the logic transistor function (LTF), that was devised to model the static CMOS combinational circuits at the transistor and logic level, to model the dynamic CMOS combinational circuits. The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault-free LTF using a systematic procedure. The model assumes the following logic values (0, 1, I, M), where I, and M imply an indeterminate logical value, and a memory element, respectively. The model is found to be efficient in describing a cluster of dynamic CMOS circuits at both the fault-free and faulty modes of operation. Both single and multiple transistor stuck faults are precisely described using this model. The classical stuck-at and non classical stuck open and short faults are analyzed. A systematic procedure to produce the fault-free and faulty LTFs for different implementations of the dynamic CMOS combinational circuits is presented.     

A novel digital logic implementation approach on nanocrossbar arrays using memristor-based multiplexers

This paper presents and evaluates a novel multiplexer (MUX) composed of memristive devices and nanowire crossbar arrays. The switching behavior of memristors is employed to reveal the desired output state. By applying a sequence of appropriate voltage pulses to the developed MUX, the output is derived and can be transferred through read/write CMOS circuitry. The performance is verified with the SPICE simulator including a threshold-type memristor model. Using the proposed MUXes instead of memristor-based NAND gates, the routing effects that are a major challenge for implementing combinational logic in hybrid circuits can be reduced. Our evaluation results show that both density and delay are effectively improved in pure-MUX-based fabrics.     

Analysis of High-Performance Fast Feedthrough Logic Families in CMOS

This brief presents a new CMOS logic family using the feedthrough evaluation concept and analyzes its sensitivity against technology parameters for practical applications. The feedthrough logic (FTL) allows for a partial evaluation in a computational block before its input signals are valid, and does a quick final evaluation as soon as the inputs arrive. The FTL is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, FTL based circuits perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low-power FTL provides for smaller propagation time delay (4.1 times), lower energy consumption (35.6%), and similar combined delay, power consumption and active area product (0.7% worst), while providing lower sensitivity to power supply, temperature, capacitive load and process variations than the standard CMOS technologies.     

CMOS circuit optimization

In this paper, optimization algorithms for CMOS circuits are described, from the propagation delay time viewpoint. The propagation delay time for a CMOS in erter is calculated for a step function input. A classical model of I–V characteristics for a MOSFET and the worst case Sah model for inter-electrode capacitances of a MOSFET are used for this deduction.     

Study of Scaling Trends in Energy Recovery Logic: An Analytical Approach

This paper presents an analytical model to study the scaling trends in energy recovery logic. The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage, device threshold voltage and gate oxide thickness. The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale. This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.