移动数字信号基带处理平台的设计与实现

设计了基于ARM,DSP和FPGA多处理器的分时长期演进系统(TD-LTE)移动数字信号基带处理平台。该处理平台能够灵活实现移动通信中基带信号的各种操作,主要功能模块包括协议软件实现、物理层算法实现、系统定时等。经测试,在LTE模式及20 MHz带宽下,平台符合LTE标准技术指标要求,验证了其实时性、高效性。另外,该基带处理平台从硬件设计上还满足TD-SCDMA,WCDMA,CDMA2000等各种无线通信系统的数字信号处理需求,只需适当修改部分软件,即可实现多种制式的基带处理功能,具有良好的通用性。     

Exploiting Thread‐Level Parallelism in Lockstep Execution by Partially Duplicating a Single Pipeline

In most parallel loops of embedded applications, every iteration executes the exact same sequence of instructions while manipulating different data. This fact motivates a new compiler‐hardware orchestrated execution framework in which all parallel threads share one fetch unit and one decode unit but have their own execution, memory, and write‐back units. This resource sharing enables parallel threads to execute in lockstep with minimal hardware extension and compiler support. Our proposed architecture, called multithreaded lockstep execution processor (MLEP), is a compromise between the single‐instruction multiple‐data (SIMD) and symmetric multithreading/chip multiprocessor (SMT/CMP) solutions. The proposed approach is more favorable than a typical SIMD execution in terms of degree of parallelism, range of applicability, and code generation, and can save more power and chip area than the SMT/CMP approach without significant performance degradation. For the architecture verification, we extend a commercial 32‐bit embedded core AE32000C and synthesize it on Xilinx FPGA. Compared to the original architecture, our approach is 13.5% faster with a 2‐way MLEP and 33.7% faster with a 4‐way MLEP in EEMBC benchmarks which are automatically parallelized by the Intel compiler.     

一种新型多媒体SoC验证平台原理及其实现

提出了一种基于ADSP-BF537的新型多媒体SoC验证平台,以满足多媒体SoC音视频编解码功能模块的实时验证。介绍了整个平台的基本组成,以及BF537与SoC接口的软硬件设计;最后,以验证用于SoC的MP3硬件解码器模块为例,讨论了如何利用BF537,在多媒体SoC的FPGA原型内进行软硬件协同验证。该验证方案已经成功应用在深圳艾科创新微电子有限公司的一款多媒体SoC设计流程中。     

基于Motorola DSP的数字音效处理系统

提出一种基于Motorola DSP56364的数字音效处理系统的设计方案。文中首先讨论数字音频系统设计需要注意的事项，接着分析DSP56364的ESAI接口通过I^2S协议与外部A／D、D／A进行无缝连接的问题，并给出系统的流程和硬件结构框图。最后以典型的回声音效算法为例，说明基于该系统平台的软件处理流程。实验表明在该系统平台上可以很好的运行多种音效处理算法。     

Pipelined Scheduling of Functional HW/SW Modules for Platform‐Based SoC Design

We developed a pipelined scheduling technique of functional hardware and software modules for platform‐based system‐on‐a‐chip (SoC) designs. It is based on a modified list scheduling algorithm. We used the pipelined scheduling technique for a performance analysis of an MPEG4 video encoder application. Then, we applied it for architecture exploration to achieve a better performance. In our experiments, the modified SoC platform with 6 pipelines for the 32‐bit dual layer architecture shows a 118% improvement in performance compared to the given basic SoC platform with 4 pipelines for the 16‐bit single‐layer architecture.     

可重用AVS芯片结构软硬件协同设计

根据软硬件设计思想设计一个结构划分合理的可重用的AVS视频解码器结构.通过ARM平台软件移植,然后使用ARM ESL工具对系统模块性能进行整体评估,然后根据评估结果以及硬件实现复杂度进行软硬件结构的划分,定制软硬件模块接口,从硬件扩展考虑把硬件部分设计为与H.264解码器兼容并用SystemC模拟,最后在SOC Designer 平台做协同验证及仿真.     

A Fully Synthesizable Bluetooth Baseband Module for a System‐on‐a‐Chip

Bluetooth is a specification for short‐range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area‐efficient digital baseband module for wireless technology. For area‐efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware‐efficient functions, such as low‐level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB) interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core on system‐on‐a‐chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a 0.25‐µm CMOS technology, the core size of which was only 2.79 mm×2.80 mm.     

基于DVB的数据广播

主要介绍了在DVB数据广播标准中数据信息的多种传输方式，然后阐述了DVB数据广播的分层结构及其试验平台的软硬件实现。     

基于DSP的红外搜索跟踪系统软件设计

针对双波段红外搜索跟踪系统任务需求,基于多核DSP的通用信号处理硬件平台,结合系统功能需求、算法需求及多核DSP硬件特征,设计了一种基于主从架构的多核DSP软件架构,并完成了搜索跟踪算法与应用软件的设计与实现,在红外搜索跟踪系统中进行了应用验证,试验证明,该技术可以满足系统对红外双波段图像任务功能的实时处理需求。     

Digital Audio Effect System‐on‐a‐Chip Based on Embedded DSP Core

This paper describes the implementation of a digital audio effect system‐on‐a‐chip (SoC), which integrates an embedded digital signal processor (DSP) core, audio codec intellectual property, a number of peripheral blocks, and various audio effect algorithms. The audio effect SoC is developed using a software and hardware co‐design method. In the design of the SoC, the embedded DSP and some dedicated hardware blocks are developed as a hardware design, while the audio effect algorithms are realized using a software centric method. Most of the audio effect algorithms are implemented using a C code with primitive functions that run on the embedded DSP, while the equalization effect, which requires a large amount of computation, is implemented using a dedicated hardware block with high flexibility. For the optimized implementation of audio effects, we exploit the primitive functions of the embedded DSP compiler, which is a very efficient way to reduce the code size and computation. The audio effect SoC was fabricated using a 0.18 μm CMOS process and evaluated successfully on a real‐time test board.     

Evolution of satellite communications: Integration of ETSI BSM and DVB‐RCS for future satellite terminals

The main added value of the European Telecommunications Standards Institute broadband satellite multimedia (ETSI BSM) architecture is the definition of the Satellite Independent‐Service Access Point (SI‐SAP) protocol interface, which formally separates Satellite Dependent (SD) from SI layers, thus enabling the implementation of powerful vertical QoS mapping strategies. On the other hand, DVB‐S2/RCS satellite standard is considered the driving technology to integrate satellite with terrestrial infrastructure and provide up‐to‐date services. This paper focuses on the integration of ETSI BSM architecture and DVB‐RCS technology, by analysing the adaptations needed on real DVB‐RCS terminals to be interoperable with the SI‐SAP interface. To this end, the detailed design of an underlying architecture taking into account required adaptations and new functionalities is proposed. The possible further evolutions of the BSM specification are also highlighted, showing the potential for the development of future devices integrating both DVB‐RCS and ETSI BSM architectures also in view of the recent upgrade to the DVB‐RCS2 standard. The paper also validates the SI‐SAP QoS functionalities and proves the performance benefits in terms of QoS and quality of experience of Web‐browsing by means of a satellite emulator developed fors this aim. Copyright © 2015 John Wiley & Sons, Ltd.     

SVM‐Based Speaker Verification System for Match‐on‐Card and Its Hardware Implementation

Using biometrics to verify a person's identity has several advantages over the present practice of personal identification numbers (PINs) and passwords. To gain maximum security in a verification system using biometrics, the computation of the verification as well as the storing of the biometric pattern has to take place in a smart card. However, there is an open issue of integrating biometrics into a smart card because of its limited resources (processing power and memory space). In this paper, we propose a speaker verification algorithm using a support vector machine (SVM) with a very few features, and implemented it on a 32‐bit smart card. The proposed algorithm can reduce the required memory space by a factor of more than 100 and can be executed in real‐time. Also, we propose a hardware design for the algorithm on a field‐programmable gate array (FPGA)‐based platform. Based on the experimental results, our SVM solution can provide superior performance over typical speaker verification solutions. Furthermore, our FPGA‐based solution can achieve a speed‐up of 50 times over a software‐based solution.     

一种新型单片机/ARM/DSP实验装置的研制

本文介绍了一种新开发的单片机/ARM/DSP实验装置。该装置由核心板、通用板和扩展板构成,可插用多种CPU芯片进行实验。学生可利用本装置方便地开展自主性的设计和实验,十分有利于发挥想象力和创造力,提高其硬件设计和软件调试的能力。文中特别介绍了装置的ARM核心板的设计以及在Proteus虚拟硬件平台上进行ARM实验软件仿真调试的方法。     

基于ARM+DSP的钢琴调律器设计

针对钢琴调律工作的特点,结合现代数字信号处理技术和嵌入式技术,提出了基于ARM和DSP双处理器的钢琴调律器的设计思路.选用音频编解码芯片TLV320AIC23对琴音信号采集;采用以TMS320VC5402为核心的信号处理模块完成信号处理算法实现,包括基频的提取、基频范围的确定、采样率自适应变换以及调音判断等;利用以S3...     

DSP实现DVB信道编解码

概述了DVB标准,介绍一种采用高速通用DSP的实时信道编解码的实现方案.系统以TI通用DSP TMS320C6712为主处理器,配合小型CPLD的逻辑控制,硬件和软件设计充分利用了DSP的特点.由于系统规范主要由DSP软件实现,因而能通过修改软件以适合不同的应用场合.系统具有完备的调试电路和良好的可维护性.     

基于ARM ESL的AVS亮度插值的软硬件协同的研究

提出一种基于ARM ESL平台的软硬件协同的设计方法,并进行了整个AVS解码系统的设计和仿真验证.在具体的软硬件划分中,通过采用硬件加速AVS亮度插值模块,合并了二分与四分之一亮度插值的软件算法, 并用DMA控制器改进插值的硬件结构,从而改善了系统的整体性能.实验中比较十帧720x576的AVS解码图像在原始纯软件环境,同软硬件协同系统的仿真结果.仿真结果说明新的AVS解码系统的体系结构提高了AVS解码系统的整体性能,为AVS系统的软硬件协同设计提供了有益的参照.     

基于ARM SoC的FPGA原型验证

ARM是目前SoC设计中应用最为广泛的高性价比的RISC处理器,FPGA原型验证是SoC有效的验证途径,FPGA原型验证平台能以实时的方式进行软硬件协同验证,从而可以缩短SoC的开发周期,提高验证工作的可靠性,降低SoC系统的开发成本.     

一种公共的多DSP硬件模块实现方法

简单介绍了多DSP硬件模块的应用背景。主要介绍了基于美国德州仪器(TI)公司生产的TMS320 VC5416 DSP芯片实现的8 DSP硬件模块实现方法。该模块的结构主要包括多片DSP、FLASH程序加载、JTAG硬件仿真和FPGA等子模块。详细论述了多DSP与FPGA的连接、FLASH存储器与DSP、FPGA的连接,以及硬件仿真所用的JTAG菊花链。并且通过验证该硬件模块运行正确。     

基于FPGA与Cortex—M3的仿真验证平台设计

本文主要介绍基于xillaxK7系列FPGA与ARMCortexM3处理器设计的可用于仿真与芯片验证的综合平台。本文结合FPGA与ARMCortexM3处理器的技术特点,着重描述了该平台的软硬件设计与应用场合,并介绍了平台实际使用情况。     

基于Linux/Qt和WiFi无线传输的数据采集系统

针对远程通信和轻小便携的数据采集系统的需求,设计了一种新型的数据采集系统。采用以ARM9处理器S3C2440为核心的硬件平台和以Linux系统为核心的软件平台,在此基础上采用Qt技术开发控制界面的应用程序。通过WiFi模块和USB实现了ARM与数据采集设备的两种通信方式,具有参数设置、参数回读、数据采集和存储及数据显示的功能。该系统具有操作简单,反应灵敏,轻小便携等特点。经实验证明,系统具有良好的可靠性和稳定性。重点介绍系统软件的开发及实现。