Dynamic positive feedback source-coupled logic (D-PFSCL)

This paper presents dynamic positive feedback source-coupled logic (D-PFSCL) style which is derived from positive feedback source-coupled logic (PFSCL). The proposed logic style uses dynamic current source in contrast to constant current source of PFSCL to attain lower power consumption. Two techniques for D-PFSCL style-based multistage applications are suggested. Several D-PFSCL gates are simulated and compared with the respective PFSCL counterparts through SPICE simulations by using Taiwan semiconductor manufacturing company 0.18 µm CMOS technology parameters. A maximum power reduction of 84% is achieved for D-PFSCL gates. The effect of process variation on the power consumption of the D-PFSCL gates shows a maximum variation factor of 1.5 between the best and the worst cases.     

Emitter function logic-logic family for LSI

A highly efficient large-scale integration logic family combining the advantages of multiemitter structures with the performance of emitter-coupled logic is discussed. Simplified gate structure has been found to reduce propagation delay, power and number of logic levels required for logic function realization. Conventional processing affords 2-5-pJ performance. The principle of operation of a basic AND-OR gate is shown and compared with the well known ECL gate. Fundamental gating and sequential logic functions are compared with the conventional inverting designs. The solid-state realization of a test gate is described. The speed-power performance advantage of emitter function logic gates and functions are contrasted with those of presently popular logic families.     

RSYN: a system for automated synthesis of reliable multilevelcircuits

Conventional logic synthesis systems are targeted towards reducing the area required by a logic block, as measured by the literal count or gate count; or, improving the performance in terms of gate delays; or, improving the testability of the synthesized circuit, as measured by the irredundancy of the resultant circuit. In this paper, we address the problem of developing reliability driven logic synthesis algorithms for multilevel logic circuits, which are integrated within the MIS synthesis system. Our procedures are based on concurrent error detection techniques that have been proposed in the past for two level circuits, and adapting those techniques to multilevel logic synthesis algorithms. Three schemes for concurrent error detection in a multilevel circuit are proposed in this paper, using which all the single stuck at faults in the circuit can be detected concurrently. The first scheme uses duplication of a given multilevel circuit with the addition of a totally self-checking comparator. The second scheme proposes a procedure to generate the multilevel circuit from a two level representation under some constraint such that, the Berger code of the output vector can be used to detect any single fault inside the circuit, except at the inputs. A constrained technology mapping procedure is also presented in this paper. The third scheme is based on parity codes on the outputs. The outputs are partitioned using a novel partitioning algorithm, and each partition is implemented using a multilevel circuit. Some additional parity coded outputs are generated. In all three schemes, all the necessary checkers are generated automatically and the whole circuit is placed and routed using the Timberwolf layout package. The area overheads for several benchmark examples are reported in this paper. The entire procedure is integrated into a new system called RSYN     

FAULT DETECTION TEST SET FOR TESTABLE REALIZATIONS OF LOGIC FUNCTIONS WITH ESOP EXPRESSIONS

The circuit testable realization and its fault detection for logic functions with ESOP （EXOR-Sum-Of-Products） expressions are studied. First of all, for the testable realization by using XOR gate cascade, a test set with 2n ＋ m ＋ 1 vectors for the detections of AND bridging faults and a test set with 2n ＋ m vectors for the detections of OR bridging faults are presented. Secondly, for the testable realization by using ）（OR gate tree, a test set with 2n ＋ m vectors for the detections of AND bridging faults and a test set with 3n ＋ m ＋ 1 vectors for the detections of OR bridging faults are presented. Finally, a single fault test set with n ＋ 5 vectors for the XOR gate tree realization is presented. Where n is the number of input variables and m is the number of product terms in a logic function.     

An efficient triple-tail cell based PFSCL D latch

In this paper, an efficient positive feedback source-coupled logic (PFSCL) D latch topology is proposed. It uses triple-tail cell concept which results in lesser number of stages as well as gate count in comparison to the traditional PFSCL D latch. The operation of the proposed D latch is described and is supported with mathematical formulations. The functionality is verified through SPICE simulations using TSMC 0.18 µm CMOS technology parameters. It is found that the proposed D latch topology significantly reduces the power consumption and delay in comparison to the traditional PFSCL D latch. The impact of process variation on the proposed and traditional PFSCL D latch at different design corners shows similar variations.     

A charge-transfer-device logic cell

A logic scheme capable of performing AND-OR logic functions using charge-transfer devices is presented in this paper. Applications of the logic cell are discussed. A half-adder, a ‘flip-flop’, a majority logic gate, an analog-to-digital and a digital-to-analog converter are obtained by extending or modifying the basic scheme. An integrated MOS BBD realization of the AND-OR logic cell is described in detail. Experimental results are presented and shown to be in agreement with theoretical calculations.     

能量回收电容耦合逻辑及其综合方法

提出了一种新型能量回收电路ERCCL(能量回收电容耦合逻辑),该电路的能耗低于传统CMOS电路及其他能量回收电路.ERCCL利用电容耦合进行逻辑求值,因此可以在一个门中低能耗地实现高扇入、高复杂度的逻辑.同时ERCCL是一种阈值逻辑.所以一个基于ERCCL的系统可以大大减少逻辑门数,从而降低系统能耗.针对ERCCL提出了一种阈值逻辑综合方法.用基准电路集MCNC做了相应的实验.与SIS的综合结果相比,该方法大约减少80%的逻辑门.     

能量回收电容耦合逻辑及其综合方法

提出了一种新型能量回收电路ERCCL（能量回收电容耦合逻辑）,该电路的能耗低于传统CMOS电路及其他能量回收电路．ERCCL利用电容耦合进行逻辑求值,因此可以在一个门中低能耗地实现高扇入、高复杂度的逻辑．同时ERCCL是一种阈值逻辑．所以一个基于ERCCL的系统可以大大减少逻辑门数,从而降低系统能耗．针对ERCCL提出了一种阈值逻辑综合方法．用基准电路集MCNC做了相应的实验．与SIS的综合结果相比,该方法大约减少80％的逻辑门．     

Noise Analysis of Soft Errors in Combinational Digital Circuits Via Walsh Transforms

The noise produced at the output of combinational logic circuits by individual gate failures is analyzed through the use of Walsh functions. Soft errors are modeled by allowing the output of each gate in a particular realization to fail temporarily, possibly introducing an error in the single binary output. The input variables also are allowed to be stochastically driven. The output probability of error contains the Walsh transform of an extended logic function and the Walsh characteristic functions of the input variables as well as the individual gate failure variables. These results are specialized to the case where the inputs are statistically independent of the soft errors. A discussion of the transform of the extended logic function is included.     

Novel pipeline architectures based on Negative Differential Resistance devices

Devices exhibiting Negative Differential Resistance (NDR) in their I–V characteristic are attractive from the design point of view and circuits exploiting it have been reported showing advantages in terms of performance and/or cost. In particular, logic circuits based on the monostable to bistable operating principle can be built from the operation of two series connected NDR devices with a clocked bias. Monostable to Bistable Logic Element (MOBILE) gates allow compact implementation of complex logic function like threshold gates and are very suitable for the implementation of latch-free fine grained pipelines. This pipelining relies on the self-latching feature of MOBILE operation. Conventionally, MOBILE gates are operated in a gate level pipelined fashion using a four-phase overlapped clock scheme. However other simpler, and higher through-output interconnection schemes are possible. This paper describes latch-free MOBILE pipeline architectures with a single clock and with a two phase clock scheme which strongly rely on distinctive characteristics of the MOBILE operating principle. Both the proposed architectures are analyzed and experimentally validated. The fabricated circuits use a well-known transistor NDR circuit (MOS-NDR) and an efficient MOBILE gate topology built on its basis. Both solutions are compared and their distinctive characteristics with respect to domino based solutions are pointed out.     

采用vMOS管的多值计数器设计

通过对νMOS管特性和多值逻辑电路设计原理的研究,本文提出一种新型多值计数器的设计方案。该方案利用νMOS管具有多输入栅加权信号控制及浮栅上的电容耦合效应等特性,结合二值逻辑编码方法,实现电路的多值输出。用PSPICE对所设计的电路模拟验证,结果表明,所设计的电路逻辑功能正确,结构简单,功耗低,且通用性强,易于实现。     

基于组合逻辑电路实现方法的探究

为缩短理论与实践的距离,提高灵活应用数字元器件的能力,提出了组合逻辑电路设计的第五步.组合逻辑电路设计通常有四步,设计完成画出符合功能要求的逻辑图,一般是把其转换成TrL与非门形式的逻辑图.第五步研究用多少个、何种逻辑门、译码器、数据选择器,怎样实现组合逻辑电路.实践证明,只要把逻辑电路与选择实现功能器件相互对应输入输...     

Multiple-input and -output OR/AND circuits for VLSI GaAs IC's

OR/AND circuits with multiple input and output have been demonstrated experimentally for low-power 2K and 6K GaAs gate arrays with two levels of logic at approximately a 155-percent increase in speed and power product. The proposed multiple-logic levels process in parallel some complex logic functions with only one gate delay. Two proposed bootstrap techniques have shown an improvement of typically 12 percent in speed without an increase in power for low-power applications. In coupling these OR/AND circuits with the allowable buffered stage and the bootstrap enhancements, one can obtain good device performance over a spectrum of SSI to VLSI in the SDFL circuit family.     

基于高非线性Sagnac干涉仪的超高速全光NOT门可级联性研究

在未来的通信领域中,全光逻辑门是全光计算机和全光网络的基本单元。目前已经提出了很多实现全光逻辑门的结构和方法,但是全光逻辑的技术瓶颈也出现了,就是怎样能够将单个的全光逻辑门级联起来实现更复杂的逻辑关系。现存的全光逻辑门结构一般不具有很好的可以实现多级连接的级联性,而且现有的对于级联性的分析大都停留在理论层面,而没有与实际情况相结合,所以对于实际应用来说意义很小。提出了一种新型的基于高非线性Sagnac 干涉仪的超高速全光NOT 门,建立了它的数学模型,采用了与实际情况更加接近的高斯脉冲模拟输入光,并且在仿真结果的基础上分析了系统的级联性,对级联性的分析考虑了光纤损耗和走离效应的影响。得到的基本结论表明,所提出的全光逻辑门的结构能够在实际情况下保持良好的级联性。     

Ultrahigh-speed logic gate family with Nb/Al-AlOx/Nb Josephson junctions

The modified variable threshold logic (MVTL) OR gate has a wide operating margin and occupies a small area, so that a gate family using this OR gate is suitable for LSI logic circuits. This paper describes the design, fabrication process, and evaluation of the MVTL gate family. The gate family is composed of OR, AND, and 2/3 MAJORITY gates. The gates were made with all refractory material including Nb/ Al-AlOx/Nb junctions and Mo resistors, and they were patterned by using a reactive ion etching (RIE) technique. The logic delay of the gate was measured with a Josephson sampler. The minimum delays for OR, AND, and 2/3 MAJORITY gates were 5.6, 16, and 21 ps/gate, respectively.     

An opportunistic relaying‐based incremental hybrid DAF cooperative system

In this paper, an opportunistic relaying‐based incremental hybrid decode‐amplify‐forward (OR‐IHDAF) scheme that combines robust protocol switch with efficient relay selection is proposed in multi‐relay scenario to cope with the complex and variable channel environments. The proposed OR‐IHDAF scheme can improve the system performance significantly compared with the incremental hybrid decode‐amplify‐forward protocol with the increase of the possible candidate relay nodes and opportunistic relay selection. The analytical expression of the system outage probability of the OR‐IHDAF scheme is presented based on the probability density function and cumulative distribution function, which might be useful to avoid lengthy simulations. Numerical results show the correctness of our theoretical analysis and the performance improvement of the OR‐IHDAF scheme compared with the other current hybrid cooperative protocols and OR‐based cooperative schemes. The effects of the power allocation schemes on the outage probability are also provided. Copyright © 2015 John Wiley & Sons, Ltd.     

MOSFET-like CNFET based logic gate library for low-power application: a comparative study

The next generation of logic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLSI. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average power-delay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.     

一种网站分析系统的设计方案

随着网络技术的高速发展,各类网站也得到迅猛发展。由于网络容易受到各方面的攻击,并且经常发生故障,所以如何对Web网站运行状态、网站整体性能变化趋势进行监控和分析显得尤为重要。本文提出了一种网站分析系统的设计方案,具体包括一个稳定高效的网络爬虫机制对定制的网站进行定时整站爬取、构造网站整体结构逻辑图、分析网站整体性能并提供告警机制等,最后详细介绍了网络分析系统的设计思路和各个组成部分的实现方案。     

Josephson dual rail two-bit adder circuit utilizing magnetically coupled OR-AND gates

A novel Josephson logic gate called the asymmetrical interferometer device (AID) is presented. It is composed of a pair of asymmetrical interferometers whose outputs are injected into a single junction. The interferometers are individually operated as two input OR and the single junction is worked as AND.(A + B) (C + D)operation is accomplished by only one AID gate. They have a serial fan-in capability due to their magnetic coupling scheme. The gate size is reduced by half, compared with the previous current injection logic (CIL) gate. With these AID gates, a high-speed two-bit dual rail adder circuit is configured, which provides the logic circuits performing with both true and complement inputs and without any timing circuits. The AID gate fabricated by standard 5-µm Pb-alloy technology showed a wide margin over ±20 percent that was in good agreement with statically designed characteristics. Experimental adder operation was also successfully performed.     

Functional devices based on real space transfer in Si/SiGestructure

A charge injection transistor, which operates as an exclusive-OR logic gate, and a monolithic multiterminal device, electrically reprogrammable between OR and NAND logic function, have been successfully implemented in a Si-Si_0.7Ge_0.3 heterostructure grown by rapid thermal epitaxy on a Si substrate. Room temperature operation of the charge injection transistor is demonstrated, with 10 dB on/off ratio for the exclusive-OR logic function. Microwave measurements indicate a short circuit current gain cutoff of 6 GHz, for a device with a source-drain distance of 0.5 μm. Device simulations were used to identify primary dependencies of the device performance on the parameters used in the design of the structure. Further structural improvements are suggested