能量回收电容耦合逻辑及其综合方法

提出了一种新型能量回收电路ERCCL(能量回收电容耦合逻辑),该电路的能耗低于传统CMOS电路及其他能量回收电路.ERCCL利用电容耦合进行逻辑求值,因此可以在一个门中低能耗地实现高扇入、高复杂度的逻辑.同时ERCCL是一种阈值逻辑.所以一个基于ERCCL的系统可以大大减少逻辑门数,从而降低系统能耗.针对ERCCL提出了一种阈值逻辑综合方法.用基准电路集MCNC做了相应的实验.与SIS的综合结果相比,该方法大约减少80%的逻辑门.     

能量回收阈值逻辑及其功率时钟产生电路

提出了能量回收阈值逻辑电路(ERTL).该电路把阈值逻辑应用到绝热电路中,降低能耗的同时也降低了电路的门复杂度.并且提出了一种高效率的功率时钟产生电路.该功率时钟电路能够根据逻辑的复杂度和工作频率,调整电路中MOS开关的开启时间,以取得最优的能量效率.为了便于功率时钟的优化设计,推导出了闭式结果.基于0.35μm的工艺参数,设计并且仿真了ERTL可编程逻辑阵列(PLA)和普通结构PLA.在20～100MHz的工作频率范围内,提出的功率时钟电路的能量效率可以达到77%～85%.仿真结果还显示,ERTL是一个低能耗的逻辑.ERTLPLA与普通结构的PLA相比,包括功率时钟电路的     

能量回收阈值逻辑及其功率时钟产生电路

提出了能量回收阈值逻辑电路(ERTL).该电路把阈值逻辑应用到绝热电路中,降低能耗的同时也降低了电路的门复杂度.并且提出了一种高效率的功率时钟产生电路.该功率时钟电路能够根据逻辑的复杂度和工作频率,调整电路中MOS开关的开启时间,以取得最优的能量效率.为了便于功率时钟的优化设计,推导出了闭式结果.基于0.35μm的工艺参数,设计并且仿真了ERTL可编程逻辑阵列(PLA)和普通结构PLA.在20～100MHz的工作频率范围内,提出的功率时钟电路的能量效率可以达到77%～85%.仿真结果还显示,ERTL是一个低能耗的逻辑.ERTL PLA与普通结构的PLA相比,包括功率时钟电路的功耗在内,ERTL PLA仍节省65%～77%的功耗.     

能量回收阈值逻辑电路

通过把阈值逻辑应用在能量回收电路中,提出了一种新的电路形式——能量回收阈值逻辑电路(energyre-coverythresholdlogic,ERTL).阈值逻辑的应用,使ERTL电路的门复杂度大大降低,同时进一步降低了功耗.分别以ERTL电路和静态CMOS电路设计了4位超前进位加法器,两个加法器采用相同的结构.ERTL加法器逻辑电路的晶体管数目只占静态CMOS加法器的63%,与现有的能量回收电路相比,硬件开销减少.设计使用的是TSMC0.35μm工艺,分别在3V和5V工作电压下对电路进行Spice仿真.仿真结果显示,在实际的工作负载和工作频率范围内,ERTL电路的能耗只有静态CMOS电路的14%～58%     

能量回收阈值逻辑电路

通过把阈值逻辑应用在能量回收电路中,提出了一种新的电路形式--能量回收阈值逻辑电路(energy recovery threshold logic,ERTL).阈值逻辑的应用,使ERTL电路的门复杂度大大降低,同时进一步降低了功耗.分别以ERTL电路和静态CMOS电路设计了4位超前进位加法器,两个加法器采用相同的结构.ERTL加法器逻辑电路的晶体管数目只占静态CMOS加法器的63%,与现有的能量回收电路相比,硬件开销减少.设计使用的是TSMC 0.35μm工艺,分别在3V和5V工作电压下对电路进行Spice仿真.仿真结果显示,在实际的工作负载和工作频率范围内,ERTL电路的能耗只有静态CMOS电路的14%～58%.     

基于阈值逻辑的逻辑函数综合算法研究

阈值逻辑门由于具有强大的逻辑功能且独自构成完备集而备受关注。为了设计以阈值逻辑门为单元结构的电路,该文首先分析了谱技术与阈值函数的关系,并通过零次、一次谱系数计算阈值函数的权值和阈值。对于非阈值函数,该文提出了新的逻辑函数综合算法,可以将任意非阈值函数转化为几个阈值函数和的形式。因此,使用一个或多个阈值逻辑门组成的网络可以实现任意布尔逻辑函数。该算法为共振隧穿二极管的电路设计提供一种新方法。     

准静态单相能量回收逻辑

提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.     

准静态单相能量回收逻辑

提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.     

基于绝热逻辑的低功耗乘法器电路设计

基于绝热开关理论的能量回收逻辑与传统的静态CMOS逻辑相比,能够大大减少电路的功率消耗。这里介绍了一种使用单相正弦电源时钟的能量回收逻辑,分别用静态CMOS逻辑和这种能量回收逻辑设计,并仿真了一个两位乘法器电路,比较了这两种电路的性能。研究表明,采用能量回收逻辑设计的乘法器显著降低了电路的功率消耗。     

一种改进的能量回收逻辑电路

文本分析了能量回收电路的功耗组成，指出非绝热损失是能量回收电路的主要功耗能量来源，提出了一种改进的能量回收逻辑电路IERL。IERL电路增加了额外的回收路径，能够显著降低电路的非绝热损失，HSPICE模拟结果表明，IERL电路具有很好的低功耗性能。同时，给出了IERL电路的复杂逻辑门设计与级联方式，用0．8μm DPDM工艺实现了2位IERL全加器电路和两相正弦功率时钟电路。     

采用vMOS管的多值计数器设计

通过对νMOS管特性和多值逻辑电路设计原理的研究,本文提出一种新型多值计数器的设计方案。该方案利用νMOS管具有多输入栅加权信号控制及浮栅上的电容耦合效应等特性,结合二值逻辑编码方法,实现电路的多值输出。用PSPICE对所设计的电路模拟验证,结果表明,所设计的电路逻辑功能正确,结构简单,功耗低,且通用性强,易于实现。     

Study of Scaling Trends in Energy Recovery Logic: An Analytical Approach

This paper presents an analytical model to study the scaling trends in energy recovery logic. The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage, device threshold voltage and gate oxide thickness. The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale. This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.     

Timing-driven logic restructuring for nano-hybrid circuits

As the feature size of the integrated circuits (ICs) scales down, the future of nano-hybrid circuit looks bright in extending Moore's Law. However, mapping a circuit to a nano-fabric structure is vexing due to connectivity constraints. A mainstream methodology is that a circuit is transformed into a nano-fabric preferred structure by buffer insertion to high fan-out gates. However, it may result in timing degradation. Logic replication is a traditional way to split high fan-out gates in logic synthesis but may not be suitable for high fan-out gates with high fan-ins. In this article, a timing-driven logic restructuring framework at the gate level is proposed. The proposed framework identifies the high fan-out gates from a given gate netlist according to the fan-out threshold, following by the restructuring of high fan-out gates through the application of logic replication and buffer insertion. To improve circuit timing from a global perspective, latent critical edges are identified to avoid entrapping critical paths during the restructuring. Experimental results on ISCAS benchmarks indicate that 8.51% timing improvement and 6.13% CPU time reduction can be obtained traded with 4.16% area increase on an average.     

Design of a DTCTGAL circuit and its application

By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic (DTCTGAL) circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25 μm CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.     

Adiabatic differential voltage switch logic

To diminish the trapped charges in internal nodes of the complex logic adiabatic gate, adiabatic differential voltage switch logic (ADVSL) using capacitance coupling technique is presented. An adiabatic system, based on a relatively small number of complex ADVSL gates, reduces not only dissipation loss, but also the gate count greatly.     

基于共振隧穿二极管的阈值逻辑单元电路设计

共振隧穿二极管作为较为成熟的纳米电子器件,已被广泛应用于高速低功耗电路。由于其具有负内阻特性,单一门电路的功能大大增加,减少了电路的复杂度。在阈值逻辑函数的硬件实现方面,共振隧穿器件也体现出显著的优势。结合谱技术,基于共振隧穿二极管,设计了可实现任意三变量阈值逻辑函数的阈值逻辑单元电路。该电路还可作为阈值逻辑网络中的基本单元,实现复杂的逻辑功能。通过HSPICE软件,仿真验证了所设计电路的正确性。     

可编程光学二值双轨逻辑门

基于双轨逻辑,本文提出一种可级联的并行二值逻辑门。所有十六种二值逻辑运算可以采用偏振半波相延编程来实现。也提出了用电光晶体实现实时编程的方法。本文中给出了实验结果。     

Efficient reversible NOR gates and their mapping in optical computing domain

Reversible logic is a computing paradigm in which there is a one to one mapping between the input and the output vectors. Reversible logic gates are implemented in an optical domain as it provides high speed and low energy computations. In the existing literature there are two types of optical mapping of reversible logic gates: (i) based on a semiconductor optical amplifier (SOA) using a Mach–Zehnder interferometer (MZI) switch; (ii) based on linear optical quantum computation (LOQC) using linear optical quantum logic gates. In reversible computing, the NAND logic based reversible gates and design methodologies based on them are widely popular. The NOR logic based reversible gates and design methodologies based on them are still unexplored. In this work, we propose two NOR logic based n-input and n-output reversible gates one of which can be efficiently mapped in optical computing using the Mach–Zehnder interferometer (MZI) while the other one can be mapped efficiently in optical computing using the linear optical quantum gates. The proposed reversible NOR gates work as a corresponding NOR counterpart of NAND logic based Toffoli gates. The proposed optical reversible NOR logic gates can implement the reversible boolean logic functions with a reduced number of linear optical quantum logic gates or reduced optical cost and propagation delay compared to their implementation using existing optical reversible NAND gates. It is illustrated that an optical reversible gate library having both optical Toffoli gate and the proposed optical reversible NOR gate is superior compared to the library containing only the optical Toffoli gate: (i) in terms of number of linear optical quantum gates when implemented using linear optical quantum computing (LOQC), (ii) in terms of optical cost and delay when implemented using the Mach–Zehnder interferometer.