A Parallel-based Lifting Algorithm and VLSI Architecture for DWT

A novel Parallel-Based Lifting Algorithm （PBLA） for Discrete Wavelet Transform （DWT）, exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the critical path latency of computation, and to reduce the complexity of hardware implementation as well. The detailed derivation on the proposed algorithm, as well as the resulting Very Large Scale Integration （VLSI） architecture, is introduced, taking the 9/7 DWT as an example but without loss of generality. In comparison with the Conventional Lifting Algorithm Based Implementation （CLABI）, the critical path latency of the proposed architecture is reduced by more than half from （4Tm ＋ 8Ta）to Tm ＋ 4Ta, and is competitive to that of Convolution-Based Implementation （CBI）, but the new implementation will save significantly in hardware. The experimental results demonstrate that the proposed architecture has good performance in both increasing working frequency and reducing area.     

A High Energy-Efficient Reconfigurable VLIW Symmetric Cryptographic Processor with Loop Buffer Structure and Chain Processing Mechanism

By exploring symmetric cryptographic data level and instruction-level parallelism, the reconfigurable processor architecture for symmetric ciphers is presented based on Very-long instruction word (VLIW) structure. The application-specific instruction-set system for symmetric ciphers is proposed. As for the same arithmetic operation of symmetric ciphers, eleven kinds of reconfigurable cryptographic arithmetic units are designed by the reconfigurable technology. As to the requirement of high energy-efficient design, the loop buffer structure for instruction fetching unit is proposed to reduce the power consumption significantly with the same frequency as conventional, meanwhile, the chain processing mechanism is proposed to improve the cryptographic throughput without any area overhead. It has been fabricated with 0.18μm CMOS technology. The result shows that the processor can work up to 200MHz, and the fourteen kinds of cryptographic algorithms were mapped in the processor, the encryption throughput of AES, SNOW2.0 and SHA2 algorithm can achieve 1.19Gbps, 1.05Gbps, and 407Mbps respectively.     

Low Cost 1D DCT Core for Multiple Video Codec

The expandability of high demands for multimedia applications brings out more and more video standards for improving the coding and compression efficiency.As the most commonly used transform,Discrete cosine transform (DCT) achieves excellent energy compaction property and good compression efficiency.Hardware sharing is the mostly used efficient strategy to reduce the cost for video codec.Based on traditional matrix factorization,this paper makes three observations to direct the design of proposed hardware sharing architecture.The proposed architecture can be generally used to compute 8×8 DCT of AVS,H.264,VC-1 and HEVC in a low cost way,and can be used to decode Full-HD and WQXGA formate video sequences in real time.The design has been synthesized in 0.13μm technology.The synthesis results show that the proposed architecture achieves 76.9％ reduction in gate count,85.6％ decrease in power consumption and 35％ improvement in operational speed in comparison with other existing designs.     

Wireless Cooperative Mesh Network:A New Architecture for Network Convergence

The convergence of heterogeneous wireless networks is a trend in the evolution of wireless networks.A new architecture for network convergence,named Wireless Cooperative Mesh Network,is proposed to solve such emerging problems in convergence as transmission mode selection,load balancing,routing and handover.The new architecture is based on the structure of Wireless Mesh Networks (WMNs),and cooperative communication is also employed to further optimize its structure and upgrade its performance.It can thus obtain advantages of both the Mesh technology (high spectrum efficiency and dynamic self-organization) and cooperative communication (high diversity gain and high energy efficiency).The new architecture serves as an efficient solution for wireless network convergence.     

Node correlation clustering algorithm for wireless multimedia sensor networks based on overlapped FoVs

In this paper, a clustering algorithm is proposed based on the high correlation among the overlapped field of views for the wireless multimedia sensor networks. Firstly, by calculating the area of the overlapped field of views （FoVs） based on the gird method, node correlations have been obtained. Then, the algorithm utilizes the node correlations to partition the network region in which there are high correlation multimedia sensor nodes. Meanwhile, in order to minimize the energy consumption for transmitting images, the strategy of the cluster heads election is proposed based on the cost estimation, which consists of signal strength and residual energy as well as the node correlation. Simulation results show that the proposed algorithm can balance the energy consumption and extend the network lifetime effectively.     

一种新颖的片内高压转低压电源转换方案

A novel power supply transform technique for high voltage IC based on the TSMC 0.6μm BCD process is achieved. An adjustable bandgap voltage reference is presented which is different from the traditional power supply transform technique. It can be used as an internal power supply for high voltage IC by using the push-pull output stage to enhance its load capability. High-order temperature compensated circuit is designed to ensure the precision of the reference. Only 0.01 mm^2 area is occupied using this novel power supply technique. Compared with traditional technique, 50% of the area is saved, 40% quiescent power loss is decreased, and the temperature coefficient of the reference is only 4.48 ppm/℃. Compared with the traditional LDO （low dropout） regulator, this power conversion architecture does not need external output capacitance and decreases the chip-pin and external components, so the PCB area and design cost are also decreased. The testing results show that this circuit works well.     

Design and optimization for multiprocessor interactive GPU

In order to achieve maximization of parallelism, effective distribution of rendering tasks, balance between performance and flexibility in graphics processing pipeline, this article presents design, performance analysis and optimization for multi-core interactive graphics processing unit （MIGPU）. This processor integrates twelve processing cores with specific instruction set architecture and many sophisticated application-specific accelerators into a 3D graphics engine. It is implemented on XC6VLX550T field programmable gate array （FPGA）. MIGPU supports OpenGL2.0 with programmable front-end processor, vertex shader, plane clipper, geometry transformer, three-D clippers and pixel shaders. For boosting the performance of MIGPU, the relationship model is established between primitive types, vertices, pixels, and the effect of culling, clipping, and memory access, and shows a way to improve the speed up of the graphics pipeline. It is capable of assigning graphics rendering tasks to different processors for efficiency and flexibility. The pixel filling rate can reach to 40 Mpixel/s at its peak performance.     

Enhanced cooperative MAC for wireless local area networks

A novel network protocol,enhanced cooperative medium access control(ECoop MAC),is present in this article.Its function is to guarantee the quality of service(QoS)in wireless local area networks.For the sake of supporting different application scenarios,two proposed schemes,namely E-scheme I for lower priority traffic and E-scheme II for higher priority traffic can be adopted independently or in combination.ECoop MAC takes into account request failure problems,and utilizes cooperative protocol information to boost the system performance as well as to effectively cut control packets overhead.Simulation results show that the proposed algorithm can not only improve network throughput,but also lead to reduced network delays for individual packets.     

User association and resource allocation in green mobile edge networks using deep reinforcement learning

In order to meet the emerging requirements for high computational complexity, low delay and energy consumption of the 5th generation wireless systems (5G) network, ultra-dense networks (UDNs) combined with multi-access edge computing ( MEC) can further improve network capacity and computing capability. In addition, the integration of green energy can effectively reduce the on-grid energy consumption of system and realize green computation. This paper studies the joint optimization of user association (UA) and resource allocation (RA) in MEC enabled UDNs under the green energy supply pattern, users need to perceive the green energy status of base stations (BSs) and choose the one with abundant resources to associate. To minimize the computation cost for all users, the optimization problem is formulated as a mixed integer nonlinear programming (MINLP) which is NP-hard. In order to solve the problem, a deep reinforcement learning ( DRL)-based association and optimized allocation (DAOA) scheme is designed to solve it in two stages. The simulation results show that the proposed scheme has good performance in terms of computationcost and time out ratio, as well achieve load balancing potentially.     

AN ADAPTIVE FEC SCHEME FOR Ka-BAND SATELLITE COMMUNICATIONS

Rain attenuation is the major problem for Ka-band satellite communications, and the fading due to rain can be well described by a lognormally distributed, first-order autoregressive model. Forward Error-control Coding (FEC) techniques can be used to reduce the effect of the rain attenuation, but the use of FEC causes a reduction in the bandwidth efficiency. In order to increase the bandwidth efficiency as well as maintain high link availability, an Adaptive Forward Error-control Coding (AFEC) scheme with rain fading prediction is proposed and analyzed in this paper. The results show that AFEC offers a good trade-off between link availability and bandwidth efficiency.     

Analysis and Design of Multi-aspect SAR System for Compressive Sensing-Based 3D Imaging

This paper focuses on the analysis and design of Multl-aspect SAR （MuSAR） system for Compressive sensing-based （CS-based） 3D imaging. For this purpose,the Point ambiguous function （PAF） is proposed to analyze the factors that dominate the Mutual coherence （MC） of MuSAR sensing matrix. The PAF contacts with the parameters and configuration of MuSAR system directly and is easy to manipulate. With PAF, the present study analyzes the factors that dominate the performance of CS-based MuSAR 3D imaging. First of all, the stochastic waveform is an excellent selection. Second, the angular-frequency-diversity can improve the robustness of 3D imaging. Finally, the finer sampling of received data could improve the robustness of MuSAR 3D imaging. Simulation experiments show the validity of conclusion.     

Exploring Semantic Association Rules Between Keyword and Visual Feature Clusters for Web Image Retrieval

The semantic gap is a big challenge in image retrieval area. Previous studies in web image retrieval have mainly focused on Relevance feedback （RF） and Latent semantic indexing （LSI） to alleviate the gap. This paper proposes an approach base on Frequent itemset mining （FIM） and Association rule （AR） techniques, which explores the semantic association rule between the two modalities that are represented by keyword and visual feature clusters. The rules are obtained oftline based on the inverted file, and utilized in query process online to realize the integration of the two modalities of web im- ages. Our approach improves the retrieval performance and is scalable well, as well as satisfies the requirement of the web users with no additional interactions. The exper- iments are carried out in our web image retrieval system named VAST （VisuAl ＆ SemanTic image search）, and the results show the effectiveness of the proposed approach.     

Channel Mismatches Correction in Time-Interleaved ADCs Based on Hybrid Filter Bank Reconstruction

Time-interleaved analog-to-digital con- verter （TIADC） is an efficient way to achieve higher sam- pling rate for medium-to-high resolution applications. The performance of a TIADC suffers from the mismatch errors among the sub-channels. This paper presents a method to estimate the channel mismatches using the sub-channels output data. The proposed method introduces an equiv- alent transfer function for each channel to model and es- timate the mismatch errors. A Hybrid filter bank （HFB） structure is used to both model the TIADC and recon- struct the desired uniformly sampled sequence based on the perfect reconstruction conditions of the HFB system. A four-channel 12-bit 400MHz TIADC has been imple- mented in hardware to verify the proposed calibration method. The measured results show that the Spurious- free dynamic range （SFDR） can be improved up to 74dB after being corrected with 64-tap Finite-impulse response （FIR） filters.     

Parameterized Integrated Power and Performance （PIPP） Model for Ultra High-Performance of TOPS level DSP

Amdahl＇s law is a simple and fundamen- tal tool for understanding the evolution of performance as a function of parallelism. Following a recent trend on timing and power analysis of general purpose many-core chip using this law, we develop a novel PIPP analytical model for evaluating the performance and power of hier- archical on-chip large-scale parallel architectures with the core number, super-node size, processing element number, and function unit number taken into consideration. We thereby investigate the influence of workload characteris- tics （Thread-level parallel TLP, Instruction-level parallel ILP and Data-level parallel DLP） on resource allocation with the restriction of performance and power. The re- sults provide some feasible options to design TOPS level DSP architecture as well as a theoretical basis for making the design more scalable.     

A Robust Novel Technique for SPICE Simulation of ESD Snap-back Characteristics

This paper presents a robust and novel technique for the circuit simulation of ESD （ElectroStatic discharge） snap-back characteristics. A new linearization scheme by introducing current as independent variable for the avalanche current model in ESD evaluation shows a good convergence behavior during ESD stress simulation. This technique is compatible with the traditional circuit simulator based on the Modified nodal analysis （MNA） like SPICE. We have implemented the well known Amerasekera＇s ESD MOSFET model in SPICE3fS. The commonly used ESD protection configurations such as GGNMOS （Gate-grounded NMOS） and GCNMOS （Gatecoupled NMOS） are simulated and the simulation results demonstrated the good convergence behavior of this new technique.     

Joint Antenna Selection and Robust Beamforming Design in Multi-cell Distributed Antenna System

Most of studies on Distributed Antenna System （DAS） focus on maximizing the sum capacity and perfect channel state information at transmitter （CSIT）. However, CSI is inevitable imperfect in practical wireless networks. Based on the sources of error, there are two models. One assumes error lies in a bounded region, the other assumes random error. Accordingly, we propose two joint antenna selection （AS） and robust- beamforming schemes aiming to minimize the total transmit power at antenna nodes subject to quality of service （QoS） guarantee for all the mobile users （MUs） in multicell DAS. This problem is mathematically intractable. For the bounded error model, we cast it into a semidefinite program （SDP） using semidefinite relaxation （SDR） and S-procedure. For the second, we first design outage constrained robust beamforming and then formulate it as an SDP based on the Bernstein-type inequality, which we generalize it to the multi-cell DAS. Simulation results verify the effectiveness of the proposed methods.     

The Price of Anarchy of Network Coding and Routing Based on an ACS Pricing Mechanism

To emphasize the decisions of all users, and the total number of users sharing the same technique, we propose a novel Average cost sharing （ACS） pricing mechanism to study the game between Network coding （NC） and routing flows sharing a single link when users are price anticipating. We characterize the worst-case efficiency bounds of the game compared with the optimal （i.e., the Price of anarchy （PoA））, which can be as low as 4/9 when the number of routing users becomes sufficiently large. NC cannot improve the PoA significantly under ACS. However, to achieve a more efficient use of limited resources, this approach indicates the sharing users have a greater tendency to choose NC. However, the users will follow the majority users＇ choice of data transmission technique.     

NSVM Decision Tree for Multi-class Classification

A presented classification algorithm of non- linear Support vector machine （SVM） decision tree extends SVM to non-linear SVM by using kernel functions and calculates the relativity separability measure between classes after non-linear mapping. This method is introduced on the basis of the SVM decision tree. As a result, the iterative error is effectively restrained and the efficiency improved accordingly. Experimental results have shown that, compared with the original SVM decision tree algorithm, the classification rate has increased greatly and the classification time decreased apparently.     

An Enhanced IRC Algorithm for LTE Downlink Receiver in Multi-cell Environment

This paper proposes an enhanced Interfer- ence rejection combining （IRC） algorithm for Long term evolution （LTE） downlink receiver in multi-cell communi= cation systems. In this algorithm, a proper Multiple input multiple output （MIMO） receive method is adopted ac- cording to Generalized likelihood ratio test （GLRT） inter- cell interference detection. Iteration between channel es- timation and data detection is carried out to improve the performance of IRC algorithm. Simulation results show that this proposed algorithm can ei~ectively detect inter- cell interference and improve Block error rate （BLER） performance and channel estimation Mean squared error （MSE） compared to non-iterative IRC algorithm, making it suitable for LTE downlink receiver in multi-cell cellular systems.     

An SEU-Tolerant Approach for Space-Borne Viterbi Decoders

In the space environment, Viterbi decoder implemented on SRAM-based FPGA is sensitive to Single event upsets （SEUs）, which may lead to functional failure of the decoder. Conventional SEU mitigation techniques like modular redundancy could not exploit the characters of Viterbi decoders, therefore could not provide optimized SEU tolerance when the device resource utilization cost is a constraint. Leveraging the properties of the decoding algorithm, three effective mitigation techniques are adopted, including structure optimization, Error detection and correction （EDAC） for Block RAM （BRAM） protection, and Partial triple-modular redundancy （PTMR）, which are applied to the modules of the decoder in accordance with their characteristics. Analysis of effectiveness shows that compared with unmitigated design, the SEU induced failure rate in the proposed SEU tolerant decoder can be reduced to 1/4 at the cost of 61.1% extra resource utilization. Error detec- tion and correction （EDAC）.