Packaging and Assembly of 3-D Silicon Stacked Module for Image Sensor Application

This paper is for process development of assembly technologies used to fabricate the 3-D silicon carrier system-in–package (SiP). The five assembly technologies are wafer thinning, thin flip chip attach on silicon carrier, ultra low loop wire bonding, glass cap fabrication and sealing, and silicon carrier stacking. The developed SiP has three silicon carriers with four flip chip and one wire bond die chip attached to them and the carrier is stacked one above the other to form the 3-D silicon carrier SiP. Eight-inch bumped wafer thinning down to less than 100 $mu{hbox {m}}$, lower flip chip interconnect height between the chip and the carrier down to 35 $mu{hbox {m}}$, 40–50- $mu{hbox {m}}$ low loop wire bonding on overhang by direct reverse wire bonding method using 1-mil-diameter Au wire are achieved. And investigation of three types of thin film metallization systems for wirebonding and investigation of two different methods in fabricating glass cap are also studied.      

Reliability of 80 μm pitch flip chip attachment on flex

The interest toward flip chip technology has increased rapidly during last decade. Compared to the traditional packages and assembly technologies flip chip has several benefits, like less parasitics, the small package size and the weight. These properties emphasize especially when flip chip component is mounted direct to the flexible printed board. In this paper flip chip components with Kelvin four point probe and daisy chain test structure were bonded to the polyimide flex with two different types of anisotropically conductive adhesive films and one anisotropically conductive adhesive paste. The reliability of small pitch flip chip on flex interconnections (pitch 80 μm) was tested in 85°C/85% RH environmental test and −40↔+125°C thermal shock test. According to the results it is possible to achieve reliable and stable ohmic contact, even in small pitch flip chip on flex applications.     

Long time reliability study of soldered flip chips on flexible substrates

Due to the requirements of new light, mobile, small and multifunctional electronic products the density of electronic packages continues to increase. Especially in medical electronics like pace makers the minimisation of the whole product size is an important factor. So flip chip technology becomes more and more attractive to reduce the height of an electronic package. At the same time the use of flexible and foldable substrates offers the possibility to create complex electronic devices with a very high density. In terms of human health the reliability of electronic products in medical applications has top priority.In this work flip chip interconnections to a flexible substrate are studied with regard to long time reliability. Test chips and substrates have been designed to give the possibility for electrical measurements. Solder was applied using conventional stencil printing method. The flip chip contacts on flexible substrates were created in a reflow process and underfilled subsequently.The assemblies have been tested according to JEDEC level 3. The focus in this paper is the long time reliability up to 10,000 h in thermal ageing at 125 °C and temperature/humidity testing at 85 °C/85% relative humidity as well as thermal cycling (0 °C/+100 °C) up to 5000 cycles. Daisy chain and four point Kelvin resistances have been measured to characterise the interconnections and monitor degradation effects.The failures have been analysed in terms of metallurgical investigations of formation and growing of intermetallic phases between underbump metallisation, solder bumps and conductor lines. CSAM was used to detect delaminations at the interfaces underfiller/chip and underfiller/substrate respectively.     

纳米焦点X射线管和纳米CT检澳集成电路封装中的微型互联

IC封装中嵌入的微型电路连接可以通过纳米焦点X光光管技术和纳米焦点CT来检测：包括铜或金焊线、堆叠芯片、倒装焊接、微穿孔连接的封装形式。生动地描述了2维3维X射线影像技术,并且呈现了亚微米分辨率的各种分析结果和缺陷案例。     

纳米焦点X射线管和纳米CT检测集成电路封装中的微型互联(英文)

IC封装中嵌入的微型电路连接可以通过纳米焦点X光光管技术和纳米焦点CT来检测;包括铜或金焊线、堆叠芯片、倒装焊接、微穿孔连接的封装形式。生动地描述了2维3维X射线影像技术,并且呈现了亚微米分辨率的各种分析结果和缺陷案例。     

Highly Conductive,Flexible, Polyurethane‐Based Adhesives for Flexible and Printed Electronics

Flexible interconnects are one of the key elements in realizing next‐generation flexible electronics. While wire bonding interconnection materials are being deployed and discussed widely, adhesives to support flip‐chip and surface‐mount interconnections are less commonly used and reported. A polyurethane (PU)‐based electrically conductive adhesive (ECA) is developed to meet all the requirements of flexible interconnects, including an ultralow bulk resistivity of ≈1.0 × 10^?5 Ω cm that is maintained during bending, rolling, and compressing, good adhesion to various flexible substrates, and facile processing. The PU‐ECA enables various interconnection techniques in flexible and printed electronics: it can serve as a die‐attach material for flip‐chip, as vertical interconnect access (VIA)‐filling and polymer bump materials for 3D integration, and as a conductive paste for wearable radio‐frequency devices.     

Fatigue analysis of high-speed photodiode submodule by using FEM

Higher frequencies, super high-speed, and low-cost demands in wireless communication devices have lead to high density packaging technologies such as flip chip interconnections and multichip modules, as substitutes for wire bonding interconnection. Solder is widely used to connect chips to their packaging substrates in flip chip technology and surface mount technology. We constructed global full 3-D FE models for one photodiode on a submount to predict the fatigue life of solder interconnects during an accelerated thermal cycling testing. The 3-D FE models applied is based on the Darveaux approach does this approach have a non-linear viscoplastic analysis. In the bump structural photodiode submodule, the shortest fatigue life of 233 cycles was obtained at the thermal cycling testing condition from −65 to 150 °C. The bump material, rather than submount material, affected and varied the fatigue life. Also, The fatigue life is decreased with increase in creep strain energy density.     

Effects of Cu/Al intermetallic compound (IMC) on copper wire and aluminum pad bondability

Copper wire bonding is an alternative interconnection technology that serves as a viable, and cost saving alternative to gold wire bonding. Its excellent mechanical and electrical characteristics attract the high-speed, power management devices and fine-pitch applications. Copper wire bonding can be a potentially alternative interconnection technology along with flip chip interconnection. However, the growth of Cu/Al intermetallic compound (IMC) at the copper wire and aluminum interface can induce a mechanical failure and increase a potential contact resistance. In this study, the copper wire bonded chip samples were annealed at the temperature range from 150/spl deg/C to 300/spl deg/C for 2 to 250 h, respectively. The formation of Cu/Al IMC was observed and the activation energy of Cu/Al IMC growth was obtained from an Arrhenius plot (ln (growth rate) versus 1/T). The obtained activation energy was 26Kcal/mol and the behavior of IMC growth was very sensitive to the annealing temperature. To investigate the effects of IMC formation on the copper wire bondability on Al pad, ball shear tests were performed on annealed samples. For as-bonded samples, ball shear strength ranged from 240-260gf, and ball shear strength changed as a function of annealing times. For annealed samples, fracture mode changed from adhesive failure at Cu/Al interface to IMC layer or Cu wire itself. The IMC growth and the diffusion rate of aluminum and copper were closely related to failure mode changes. Micro-XRD was performed on fractured pads and balls to identify the phases of IMC and their effects on the ball bonding strength. From XRD results, it was confirmed that the major IMC was /spl gamma/-Cu/sub 9/Al/sub 4/ and it provided a strong bondability.     

Effect of wire diameter on the thermosonic bond reliability

Thermosonic bonding process is a viable method to make reliable interconnections between die bond pads and leads using thin gold and copper wires. This paper investigates interface morphology and metallurgical behavior of the bond formed between wire and bond pad metallization for different design and process conditions such as varying wire size and thermal aging periods. Under thermal aging, the fine pitch gold wire ball bonds (0.6 mil and 0.8 mil diameter wires) shows formation of voids apart from intermetallic compound growth. While, with 1-mil and 2-mil diameter gold wire bonds the void growth is less significant and reveal fine voids. Studies also showed void formation is absent in the case of thicker 3 mil wire bonds. Similar tests on copper ball bonds shows good diffusional bonding without any intermetallic phase formation (or with considerable slow growth) as well as any voids on the microscopic scale and thus exhibits to be a better design alternative for elevated temperature conditions.     

倒装焊技术及应用

随着集成电路封装密度的提高,传统引线键合技术已经无法满足要求,倒装焊技术的发展能够解决该问题,并且得到了广泛的应用。文章介绍了倒装焊中的4种关键工艺技术,即UBM制备技术、凸点制备方法、倒装和下填充技术。其中凸点制备技术直接决定着倒装焊技术的好坏,为满足不同产品的需求,出现了不同的凸点制备技术,使倒装焊技术具备了好的发展前景。文章对各工艺技术的应用特点进行了阐述,并对倒装焊技术的发展前景进行了展望。     

声表面波器件内连技术的发展趋势探讨

随着SAW器件向小型化、轻型化的发展,传统的引线键合技术已对其形成严重制约。倒装焊技术在30年前发展起来,它解决了器件小型化发展的问题,并与平行封焊等工艺手段一起,促进了表面贴装技术（SMT）的发展,也越来越多地用于其他工业中。文章介绍了传统线焊工艺的局限性,倒装焊工艺的核心技术以及对面临的困难可能的解决方法。     

电子封装微互连中的电迁移

 随着电子产品不断向微型化和多功能化发展,电子封装微互连中的电迁移问题日益突出,已成为影响产品可靠性和耐久性的重要因素.本文在回顾铝、铜及其合金互连引线中电迁移问题的基础上,对目前微电子封装领域广泛采用的倒装芯片互连焊点结构中电迁移问题的几个方面进行了阐述和评价,其中包括电流拥挤效应、焦耳热效应、极化效应、金属间化合物、多种负载交替或耦合作用下的电迁移以及电迁移寿命预测等.     

Flip chip interconnect systems using copper wire stud bump and leadfree solder

This research focuses on flip chip interconnect systems consisting of wire stud bumps and solder alloy interconnects. Conventional gold (Au) wire stud bumps and new copper (Cu) wire stud bumps were formed on the chip by wire stud bumping. Cu wire studs were bumped by controlling the ramp rate of ultrasonic power to eliminate the occurrence of under-pad chip cracks that tend to occur with high strength bonding wire. Lead free 96Sn3.5Ag0.5Cu (SnAgCu) alloy was used to interconnect the wire studs and printed circuit board. A comparison was made with conventional eutectic 63Sn37Pb (SnPb) alloy and 60In40Pb (InPb) alloy. Test vehicles were assembled with two different direct chip attachment (DCA) processes. When the basic reflow assembly using a conventional pick and place machine and convection reflow was used, 30% of the lead free test vehicles exhibited process defects. Other lead free test vehicles failed quickly in thermal shock testing. Applying the basic reflow assembly process is detrimental for the SnAgCu test vehicles. On the other hand, when compression bonding assembly was performed using a high accuracy flip chip bonder, the lead free test vehicles exhibited no process defects and the thermal shock reliability improved. Cu stud-SnAgCu test vehicles (Cu-SnAgCu) in particular showed longer mean time to failure, 2269 cycles for the B stage process and 3237 cycles for high temperature bonding. The C-SAM and cross section analysis of the Cu stud bump assemblies indicated less delamination in thermal shock testing and significantly less Cu diffusion into the solder compared to Au stud bumped test vehicles. The Cu stud-SnAgCu systems form stable interconnects when assembled using a compression bonding process. Moreover, Cu wire stud bumping offers an acceptable solution for lead free assembly     

Novel flip-chip bonding technology for W-band interconnections using alternate lead-free solder bumps

A novel lead-free flip-chip technology for mounting high-speed compound semiconductor ICs, which have a relatively severe limitation regarding high-heat treatment, is presented. Solder bump interconnections of 0.95Sn-0.05Au were successfully fabricated by reflowing multilayer metal film at as low a temperature as 220/spl deg/C. The bumps were designed to have a diameter of 36 /spl mu/m with a gap between the chip and the motherboard of 24 /spl mu/m. The electrical characteristics of flip-chip-mounted coplanar waveguide chips were measured. The deterioration in reflection loss in the flip chip mounting was less than 3 dB for frequencies up to W-band.     

倒装焊后清洗工艺及其对底部填充的影响

倒装焊封装是通过将整个芯片有源面进行管脚阵列排布并预制焊料凸点,通过倒装焊工艺进行互连,与传统引线键合技术相比具有更高的组装密度及信号传输速率,是实现电子产品小型化、轻量化、多功能化的关键技术之一。对于小尺寸微节距的倒装焊芯片来说,焊后清洗的难度相对更大,因此清洗技术也是影响倒装焊工艺的重要因素。针对不同清洗方式及参数的清洗效果进行对比,并研究助焊剂残留对底部填充效果的影响,以对倒装焊清洗技术进行优化。试验结果表明,利用预清洗(≥3 min)、正式清洗(≥3 min)、蒸汽漂洗(≥3 min)、真空干燥(≥4 min)的真空汽相清洗流程可充分洗净倒装焊芯片与基板细微间距中的助焊剂并且无清洗液残留,从而保证了底部填充胶的快速流动及完全固化,填充胶空洞率可达5%以下。     

Reliability of a Silicon Stacked Module for 3-D SiP Microsystem

Solder joint reliability of 3-D silicon carrier module were investigated with temperature cycle and drop impact test. Mechanical simulation was carried out to investigate the solder joint stress using finite element method (FEM), whose 3-D model was generated and solder fatigue model was used. According to the simulation results, the stress involved between flip chip and Si substrate was negligible but stress is more concentrated between Si carriers to printed circuit board (PCB) solder joint area. Test vehicles were fabricated using silicon fabrication processes such as DRIE, Cu via plating, SiO deposition, metal deposition, lithography, and dry or wet etching. After flip chip die and silicon substrate fabrication, they were assembled by flip chip bonding equipment and 3-D silicon stacked modules with three silicon substrate and flip chip dies were fabricated. Daisy chains were formed between flip chip dies and silicon substrate and resistance measurement was carried out with temperature cycle test (C, 2 cycles/h). The tested flip chip test vehicles passed T/C 5000 cycles and showed robust solder joint reliability without any underfill material. Drop test was also carried out by JEDEC standard method. More details on test vehicle fabrication and reliability test results would be presented in the paper.     

Anisotropic conductive film flip chip joining using thin chips

In this study, flip chip interconnections were made on very flexible polyethylene naphthalate substrates using anisotropic conductive film. Two kinds of chips were used: chips of normal thickness and thin chips. The thin chips were very thin, only 50 μm thick. Due to the thinness of the chips they were flexible and the entire joint was bendable. The reliability properties of the interconnections established with these two different kinds of chips were compared. In addition, the effect of bending of the chip and joint area on the joint reliability was studied. Furthermore, part of the substrates was dried before bonding and the effect of that on the joint performance was investigated.The pitch of the test vehicles was 250 μm and the chips had 25 μm high gold bumps. For resistance analysis there were two four-point measuring positions in each test vehicle. For finding the optimal bonding conditions for the test vehicles, the bonding was done using two different bonding pressures, of which the better one was chosen for the final tests.Furthermore, the test vehicles were subjected to thermal cycling tests between −40 and +125 °C (half-an-hour cycle) and to a humidity test (85%/85 °C). Part of the test vehicles were bent during the tests. Finally, the structures of the joints were studied using scanning electron microscopy.     

SMT-compatibility of adhesive flip chip on foil interconnections with 40-/spl mu/m pitch

The manufacturing and reliability of a novel type of first-level interconnections is described. Anisotropic conductive and nonconductive adhesives are used to electrically bond flip chip ICs with a pitch of 60 and 40 /spl mu/m to flexible substrates. Analyses cover the initial state of the samples as well as their performance in the JEDEC moisture sensitivity level assessment and subsequent life testing. From the different behavior of the two types of adhesives a failure mechanism issues for the reflow-soldering test.     

浅析贴片设备

由于表面组装技术不断地朝着小型化的方向发展 ,特别是在细间距、小直径的凸点和使用的焊剂等诸多因素的推动下 ,促使设备供应商根据倒装芯片技术的需求而研制新一代的贴装机。介绍了设备的制造厂家根据倒装芯片的特点 ,采用柔性 (软件 )方法和视觉系统等方案对现有的设备进行改型 ,从而实现了贴装设备的自动化。实践证明研制开发倒装芯片技术的自动组装技术可使生产率、材料和工艺设备取得明显的进步     

Flip chip on board: assessment of reliability in cellular phone application

Flip chips are generally seen as a potential future "packaging" option providing an alternative to chip scale packages. In this work, the reliability of flip chip assemblies was analyzed using daisy chain test components on a schematic test vehicle designed to emulate a cellular phone environment printed wiring board (PWB). The flip chip components were assembled in a standard surface mount technology process, where the flip chip bumps were first dipped in a flux film. A test matrix consisting of a number of flip chip test components with different input/output configurations, PWBs, fluxes, and underfills was built up. The assemblies were tested for potential damage to the flip chips and their interconnects by thermal cycling and by mechanical shock in a drop. After testing, the root causes of the failures were analyzed. As a separate task, the stress/strain generation that occurs in the flip chips in the drop test was analyzed using simulation, in order to find the critical locations on the test PWB.