基于分布估计算法的组合电路测试生成

基于遗传算法生成的测试矢量集的故障覆盖率要低于确定性方法．本文分析指出造成这种现象的一个可能原因在于，组合电路测试生成过程中存在高阶、长距离模式，从而导致遗传算法容易陷人局部极值或早熟收敛．为此，本文首次提出使用分布估计算法生成测试矢量．该方法使用联合概率分布捕捉电路主输人之间的关联性。从而避免了高阶、长距离模式对算法的影响，缓解了算法早熟收敛问题．针对ISCAS-85国际标准组合电路集的实验结果表明，该方法能够获得较高的故障覆盖率．     

一种基于神经网络的组合电路测试生成算法

介绍了一种基于神经网络的组合电路测试生成算法。利用Hopfield神经网络模型将组合电路表示成对应的神经网络,通过建立被测电路的约束网络,构造神经网络的能量函数,使组合电路的测试矢量对应神经网络能量函数的最小值点,使得测试生成问题数学化,并使用遗传算法求解能量函数的最小值点得到故障电路的测试矢量。通过在一些标准电路的实验表明,该测试生成算法有效可行。     

基于蚂蚁算法和遗传算法的时序电路测试生成

为提高时序电路的测试生成效率,该文提出一种新的基于蚂蚁算法和遗传算法的时序电路测试矢量生成算法.针对国际标准时序电路的实验结果表明,该交叉算法既充分发挥了两种算法的优点,又克服了各自的缺点,与其它同类测试生成算法相比,获得了较好的故障覆盖率和测试集.说明采用蚂蚁算法和遗传算法的交叉算法是成功的.     

时序电路测试生成新算法研究

为解决同步时序电路的测试难题,提高时序电路测试生成效率,进行了时序电路测试生成算法的研究,将粒子群优化算法应用在时序电路的测试生成中。为验证PSO算法性能,首先将其用于函数优化,能获得较好的优化结果。之后建立自动测试生成离散粒子群速度—位置模型,针对国际标准时序电路的验证结果表明,与同类算法相比,该算法可以获得较高的故障覆盖率和较小的测试矢量集。     

误差敏感竞争性学习算法

本文基于等误差准则提出了一种适用于矢量量化技术的新型码书设计算法。实验表明此算法优于现存算法。为解决初始码书赋值问题，本文提出了自生成自组织神经网络方法。实验表明此算法加速了算法的收敛速度，提高了算法的性能     

基于可配置LFSR的低功耗确定性矢量生成技术的研究

针对组合电路内建自测试过程中的功耗和故障覆盖率等问题,提出了一种能获得较高故障覆盖率的低功耗测试矢量生成方案。该方案先借助A talanta测试矢量生成工具,针对不同的被测电路生成故障覆盖率较高的测试矢量,再利用插入单跳变测试矢量的方法以及可配置线性反馈移位寄存器生成确定性测试向量的原理,获得低功耗测试矢量。通过对组合电路集ISCAS’85的实验,证实了这种测试生成方案的有效性。     

多攻击线引起的串扰时延故障的TPG

探讨了一种串扰时延最大化算法,并且利用被修改的FAN算法,生成测试矢量.对于一条敏化通路,利用被修改的FAN算法适当地激活相应的攻击线和受害线,使电路在最恶劣情况下引起最大通路时延,从而实现更有效的时延测试.利用了FAN算法的多路回退和回溯等主要特色,提高了测试生成算法的效率.实验结果表明,沿着任何临界通路传播的受害线相耦合的攻击线被适当地激活,并且可以对一定规模的电路的串扰时延故障进行测试矢量生成.     

高效的模糊聚类初始码书生成算法

码书设计在矢量量化中至关重要,而多数码书设计算法都是基于初始码书的.从经典的LBG算法的缺陷出发,提出一种基于模糊聚类的高效初始码书生成算法,通过将初始码书的码矢在输入矢量空间中很好地散开,并尽可能占据输入概率密度较大的区域,从而使之后的LBG算法避免陷入局部最优,设计出的码书性能更好,更加接近全局最优,同时加快了收敛速度,减少了迭代次数.将该算法应用于图像编码的实验中,结果表明:该算法能够从效率和质量两方面有效地提高矢量量化的性能.     

自适应矢量量化在语音识别中的应用

介绍了用离散隐马尔可夫模型(DHMM)构造孤立词语音识别系统中的特征向量矢量量化的码书构造过程。以往的矢量量化通常采用基本算法LBG,在此基础上,引入了一种时间复杂性和空间复杂性有所降低的改进算法。该算法的核心是自适应地生成初始码书以及对初始码书的二次构造过程。从降低时间复杂度和节省存储空间,提高识别率的角度,对该算法进行了讨论。     

基于标记提取的GrowCut自动分割算法

Grow Cut算法是基于细胞自动机的交互式图像分割方法,针对该算法要求用户标记初始种子需要较多工作量,且带有一定的主观性和不确定性,导致分割结果出现较大误差的问题,文中提出了简化标记,自动生成初始种子模板的基于标记提取的Grow Cut分割算法。该算法在Grow Cut算法基础上通过阈值和形态学方法预处理生成初始种子模板,运用细胞自动机迭代算法完成目标的提取。算法避免了用户人工交互约束的繁琐操作,实现了完全自动分割。通过实验对彩色图像进行自动分割,实验结果证明该算法简便、用时少,分割结果比较精确。     

一种基于大动态微波功率测量的雷达天线方向图测试方法

本文提供了一种雷达天线方向图新的测试方法,利用大动态范围的微波小功率计,最低可测量出微瓦级的功率信号,直接测量雷达天线各个方位接收到的功率信号,解决了传统的雷达天线方向图测试方法步骤繁多、测量误差大、动态范围小等不足,适用于具有良好电子对抗要求的新型低副瓣或极低副瓣雷达天线的方向图测试,完全满足工程测试的需要。     

基于变周期重播种LFSR的测试生成

基于重播种的LFSR结构的伪随机测试生成中包含的冗余测试序列较多,因而其测试序列长度仍较长,耗费测试时间长,测试效率不高。针对此状况,提出基于变周期重播种的LFSR结构的测试生成方法。该方法可以有效地跳过伪随机测试生成中的大量冗余测试序列。在保证电路测试故障覆盖率不变的条件下,缩短总测试序列的长度。分析结果表明,同定长重播种方法相比,该方法能以较少的硬件开销实现测试序列的精简,加快了测试的速度,提高了电路测试诊断的效率。     

Combined probabilistic testability calculation and compact test generation for PLAs

PLAs (programmable logic arrays) may be tested internally by self-test, or externally by applying test patterns. Fault coverage by nonexhaustive self-test is assured by computing a lower bound for estimated fault coverage vs. test pattern number. First, a lower bound for probabilistic detectability per fault is computed by a method based on Shannon's expansion theorem. In the process of finding a lower bound detectability for a particular fault, a test pattern for the fault is generated automatically, at no extra cost. These patterns often contain several don't cares. Traditional test pattern compaction is then applied to the test pattern set. In addition, a novel test pattern compaction method is introduced, suitable for embedded circuitry. The method may be used in conjunction with a serial scan architecture, whereby each test pattern is shifted one position before being applied to the circuit under test. The compaction scheme was applied to a benchmark set of 53 PLAs. An average reduction of 70% in the number of test bits and clock cycles was achieved.¹ This work was done while B. Reppen was with the Norwegian Institute of Technology.     

一种MCU的测试解决方案

对MCU进行测试时,如何高效生成测试向量是测试的难点.文章以8位MCU STC12C5410AD为例,详细地介绍了通过使用仿真环境,以C语言编写功能测试程序,完成芯片寄存器控制和主要逻辑单元运算,然后使用集成电路测试系统直接生成测试向量的解决方案.使用此解决方案,可根据测试要求,在较短时间内开发出MCU测试程序,节约测试开发成本.     

片上集成电路系统测试的新电路设计

It is very important to detect transition-delay faults and stuck-at faults in system on chip （SoC） under 90 nm processing technology, and the transition-delay faults can only be detected by using an at-speed testing method. In this paper, an on-chip clock （OCC） controller with a bypass function based on an internal phase-locked loop is designed to test faults in SoC. Furthermore, a clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by automatic test pattern generation （ATPG） tools. Next, the scan test pattern is simulated by using the Synopsys tool and the correctness of the design is verified. The result shows that the design of an at-speed scan test in this paper is highly efficient for detecting timing-related defects. Finally, the 89.29% transition-delay fault coverage and the 94.50% stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design.     

On methods to match a test pattern generator to acircuit-under-test

Autonomous circuits such as linear feedback shift registers (LFSRs) and cellular automats are used as low-cost test pattern generators for circuits testable by pseudo-random patterns. We demonstrate that different LFSRs of the same degree, started from different initial states, may yield significantly different fault coverages and test lengths when used as test pattern generators for a given circuit, especially when the circuit has faults which are hard to detect by a practical number of pseudo-random patterns. Methods to tailor an LFSR to a circuit-under-test are proposed, that attempt to select the most effective LFSR and initial state for the circuit. The first method is based on a learning process that can be applied directly to certain types of circuits. The learning process is also used to establish a collection of (primitive and nonprimitive) LFSRs and initial states, effective for arbitrary circuits. This collection can then be used as a starting point for a genetic optimization procedure aimed at improving the selected LFSR and initial state. The use of an LFSR that can apply complemented as well as uncomplemented test patterns is shown to significantly improve the fault coverage, at the cost of a small area overhead. Experimental results demonstrate the applicability of the proposed approaches to stuck-at faults and to transition faults     

一种新的直放站性能自动测试方法

对直放站性能的自动化测试在生产线和监管机构均有很高的需求。本文提出了一种通过同时控制直放站和测试仪表完成规定测试项目。从而实现自动化测试的方法。实验证明,利用这样的方法,可以对各测试项目进行无人值守的自动化测试,大幅提高测试速度,杜绝人为失误对测试结果的影响,从而提高测试的效率和准确性。     

基于VHDL语言的数字电路测试码自动生成

本文提出了一种新的基于VHDL语言的组合数字电路测试码自动生成方法。在VHDL语言描述组合数字电路的基础上,建一VHDL语言的编译器,并输入为描述被测电路的VHDL语言,输出结果为描述被测电路功能的一系列逻辑表达式。针对这些逻辑表达式,本文详细地介绍了一种能直接产生电路测试码的算法。     

基于傅立叶变换频移特性的平面近场测试方法

为了满足快速和无相测试现场天线的需求,文中提出了一种基于傅立叶变换频移特性的平面近场测 试方法。该方法采用多探头技术,利用各个通道的移相,达到天线角域的移动,实现了任意指向角信号的采集,具有 测试快速、使用便捷的特点,特别适用于天线的大规模生产测试和现场测试等。对一个标准喇叭天线进行了平面近 场扫描测量,对比了用传统近场数据处理插值方式得到的和用频移性质得到的天线远场方向图(E 面)。实验显示, 该方法具有与传统近场测试方法相同的效果,能有效地测试天线方向图。     

Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.