Field programmable gate arrays in space

The use of field programmable gate arrays (FPGAs) in satellite and other spacecraft is on the rise. They are increasingly competitive when compared to traditional application-specific integrated circuits (ASICs). However, exposure to space radiation produces the same physical effects on both FPGAs and ASICs. How these radiation effects can translate to circuit malfunctions and how these problems can be prevented or mitigated is a complex, multifaceted issue that depends on the specific technology and the device's internal architecture. First and foremost, designers should implement a reliable ASIC/FPGA development methodology for the definition, design, verification, physical implementation and validation phases of any ASIC/FPGA to be flown as part of the spacecraft platform or critical payload. This should be contractually enforced. The European Space Agency (ESA) will continue to make available its own internal standard or any other equivalent methodology proposed by the contractor. As soon as the new ECSS standard on this subject is available, ESA will start using it as an applicable document in all projects where ASICs or FPGAs are to be developed.     

Parallel scrambler for high-speed applications

In order to improve the speed limitation of serial scrambler, we propose a new parallel scrambler architecture and circuit to overcome the limitation of serial scrambler. A very systematic parallel scrambler design methodology is first proposed. The critical path delay is only one D-register and one xor gate of two inputs. Thus, it is superior to other proposed circuits in high-speed applications. A new DET D-register with embedded xor operation is used as a basic circuit block of the parallel scrambler. Measurement results show the proposed parallel scrambler can operate in 40 Gbps with 16 outputs in TSMC 0.18-/spl mu/m CMOS process.     

Security Against Hardware Trojan Attacks Using Key-Based Design Obfuscation

Malicious modification of hardware in untrusted fabrication facilities, referred to as hardware Trojan, has emerged as a major security concern. Comprehensive detection of these Trojans during post-manufacturing test has been shown to be extremely difficult. Hence, it is important to develop design techniques that provide effective countermeasures against hardware Trojans by either preventing Trojan attacks or facilitating detection during test. Obfuscation is a technique that is conventionally employed to prevent piracy of software and hardware intellectual property (IP). In this work, we propose a novel application of key-based circuit structure and functionality obfuscation to achieve protection against hardware Trojans triggered by rare internal circuit conditions. The proposed obfuscation scheme is based on judicious modification of the state transition function, which creates two distinct functional modes: normal and obfuscated. A circuit transitions from the obfuscated to the normal mode only upon application of a specific input sequence, which defines the key. We show that it provides security against Trojan attacks in two ways: (1) it makes some inserted Trojans benign, i.e. they become effective only in the obfuscated mode; and (2) it prevents an adversary from exploiting the true rare events in a circuit to insert hard-to-detect Trojans. The proposed design methodology can thus achieve simultaneous protection from hardware Trojans and hardware IP piracy. Besides protecting ICs against Trojan attacks in foundry, we show that it can also protect against malicious modifications by untrusted computer-aided design (CAD) tools in both SoC and FPGA design flows. Simulation results for a set of benchmark circuits show that the scheme is capable of achieving high levels of security against Trojan attacks at modest area, power and delay overhead.     

Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs

The latest SRAM-based FPGA devices are making the development of low-cost, high-performance, re-configurable systems feasible, paving the way for innovative architectures suitable for mission- or safety-critical applications, such as those dominating the space or avionic fields. Unfortunately, SRAM-based FPGAs are extremely sensitive to Single Event Upsets (SEUs) induced by radiation. SEUs may alter the logic value stored in the memory elements the FPGAs embed. A large part of the FPGA memory elements is dedicated to the configuration memory, whose content dictates how the resources inside the FPGA have to be used to implement any given user circuit, SEUs affecting configuration memory cells can be extremely critics. Facing the effects of SEUs through radiation-hardened FPGAs is not cost-effective. Therefore, various fault-tolerant design techniques have been devised for developing dependable solutions, starting from Commercial-Off-The-Shelf (COTS) SRAM-based FPGAs. These techniques present advantages and disadvantages that must be evaluated carefully to exploit them successfully. In this paper we mainly adopted an empirical analysis approach. We evaluated the reliability of a multiplier, a digital FIR filter, and an 8051 microprocessor implemented in SRAM-based FPGA’s, by means of extensive fault-injection experiments, assessing the capability provided by different design techniques of tolerating SEUs within the FPGA configuration memory. Experimental results demonstrate that by combining architecture-level solutions (based on redundancy) with layout-level solutions (based on reliability-oriented place and route) designers may implement reliable re-configurable systems choosing the best solution that minimizes the penalty in terms of area and speed degradation.     

Circuit-Level Design Approaches for Radiation-Hard Digital Electronics

In this paper, we present a novel circuit design approach for radiation hardened digital electronics. Our approach is based on the use of shadow gates, whose task it is to protect the primary gate in case it is struck by a heavy cosmic ion. We locally duplicate the gate to be protected, and connect a pair of diode-connected transistors (or diodes) between the outputs of the original and shadow gates. These transistors turn on when the voltages of the two gates deviate during a radiation strike. Our experiments show that at the level of a single gate, our circuit structure has a delay overhead about 1.76% on average, and an area overhead of 277%. At the circuit level, however, we do not need to protect all gates. We present a methodology to selectively protect specific gates of the circuit in a manner that guarantees radiation tolerance for the entire circuit. With this methodology, we demonstrate that at the circuit level, the average delay overhead is about 3% and the average placed-and-routed area overhead is 28%, compared to an unprotected circuit (for delay mapped designs). We also propose an improved circuit protection algorithm to reduce the area overhead associated with our approach. With this approach for circuit protection, the area and delay overheads are further lowered.      

Solving satisfiability problems using reconfigurable computing

This paper reports on an innovative approach for solving satisfiability problems for propositional formulas in conjunctive normal form (SAT) by creating a logic circuit that is specialized to solve each problem instance on field programmable gate arrays (FPGAs). This approach has become feasible due to recent advances in reconfigurable computing and has opened up an exciting new research field in algorithm design. SAT is an important subclass of constraint satisfaction problems, which can formalize a wide range of application problems. We have developed a series of algorithms that are suitable for a logic circuit implementation, including an algorithm whose performance is equivalent to the Davis-Putnam procedure with powerful dynamic variable ordering. Simulation results show that this method can solve a hard random 3-SAT problem with 400 variables within 1.6 min at a clock rate of 10 MHz. Faster speeds can be obtained by increasing the clock rate. Furthermore, we have actually implemented a 128-variable 256-clause problem instance on FPGAs     

Design and Implementation of Modular FPGA-Based PID Controllers

In this paper, modular design of embedded feedback controllers using field-programmable gate array (FPGA) technology is studied. To this end, a novel distributed-arithmetic (DA)-based proportional-integral-derivative (PID) controller algorithm is proposed and integrated into a digital feedback control system. The DA-based PID controller demonstrates 80% savings in hardware utilization and 40% savings in power consumption compared to the multiplier-based scheme. It also offers good closed-loop performance while using less resources, resulting in cost reduction, high speed, and low power consumption, which is desirable in embedded control applications. The complete digital control system is built using commercial FPGAs to demonstrate the efficiency. The design uses a modular approach, so that some modules can be reused in other applications. These reusable modules can be ported into Matlab/Simulink as Simulink blocks for hardware/software cosimulation or integrated into a larger design in the Matlab/Simulink environment to allow for rapid prototyping applications.     

Single event upset mitigation by means of a sequential circuit state freeze

This paper describes a novel design technique for hardening sequential circuits against Single Event Transients (SETs) and Single Event Upsets (SEUs) in non-volatile FPGAs. Double Modular Redundancy (DMR) is used to detect the presence of a SET in a sequential circuit. However, DMR solutions are only able to detect SET’s and not mask or correct them. Therefore, extra functionality is required to mask and correct the error after it has been detected. The central idea of the method proposed is to “freeze” the sequential circuit at a particular state when a SET is detected. As soon as the SET dissipates, the circuit is “unfrozen” so that it can continue with normal operation. Due to the short SET lifetime versus much longer circuit clock periods, the “frozen” state will normally not last more than one clock period. The proposed scheme is suitable for delay-insensitive applications requiring minimal hardware overhead.The proposed DMR method is thoroughly tested on ITC99 benchmarks. With a small delay of one clock period whenever a SET is detected, the proposed method offers immunity against the errors caused by SETs in non-volatile FPGA systems.     

一种静态随机存储器型现场可编程门阵列的单粒子软错误率的软件分析方法

静态随机存取存储器(SRAM)型现场可编程门阵列(FPGA)在当前空间电子设备中取得了广泛的应用,尽管它对空间辐射引起的单粒子翻转效应极其敏感。在FPGA的配置存储器中发生的单粒子翻转造成的失效机理不同于传统的存储器中的单粒子翻转。因此,如何评价这些单粒子翻转对系统造成的影响就成了一个值得研究的问题。传统的方法主要分为辐照实验和故障注入两种技术途径。本文中提出了一种新的方法,可以用来分析单粒子翻转对构建在FPGA上的系统造成的影响。这种方法基于对FPGA底层结构以及单粒子翻转带来的失效机理的深入理解,从布局布线之后的网表文件出发,寻找所有可能破坏电路结构的关键逻辑节点和路径。然后通过查询可配置资源与相应的配置数据之间关系来确定所有敏感的配置位。我们用加速器辐照实验和传统的故障注入方法验证了这种新方法的有效性。     

Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs

Radiation-induced soft errors are the major reliability threat for digital VLSI systems. In particular, field-programmable gate-array (FPGA)-based designs are more susceptible to soft errors compared to application-specific integrated circuit implementations, since soft errors in configuration bits of FPGAs result in permanent errors in the mapped design. In this paper, we present an analytical approach to estimate the soft error rate of designs mapped into FPGAs. Experimental results show that this technique is orders of magnitude faster than the fault injection method while more than 96% accurate. We also present a highly reliable and low-cost soft error mitigation technique which can significantly improve the availability of FPGA-mapped designs. Experimental results show that, using this technique, the availability of an FPGA mapped design can be increased to more than 99.99%.     

Object-oriented domain specific compilers for programming FPGAs

Simplifying the programming models is paramount to the success of reconfigurable computing with field programmable gate arrays (FPGAs). This paper presents a methodology to combine true object-oriented design of the compiler/CAD tool with an object-oriented hardware design methodology in C++. The resulting system provides all the benefits of object-oriented design to the compiler/CAD tool designer and to the hardware designer/programmer. The two examples for domain-specific compilers presented are BSAT and StReAm. Each domain-specific compiler is targeted at a very specific application domain, such as applications that accelerate Boolean satisfiability problems with BSAT, and applications which lend themselves for implementation as a stream architecture with StReAm. The key benefit of the presented domain specific compilers is a reduction of design time by orders of magnitude while keeping the optimal performance of hand-designed circuits     

DSP system integration and prototyping with FPGAS

Field Programmable Gate Arrays (FPGAs) offer a cost-effective and flexible technology for DSP ASIC prototype development. In this article, the fast ASIC prototyping concept based on the use of multiple FPGAs is reviewed in different engineering applications. The design experiences of the proposed approach, applied to four different DSP ASIC design projects are presented. The design experiences concerning the selection of the design methodology, application architectures and prototyping technologies are analyzed with respect to efficient system integration and ASIC migration from the FPGA prototype onto first-time functional silicon. Novel prototyping techniques based on using configurable hardware modellers concerning the same objective are studied. Some future goals are outlined to develop an integrated, multipurpose DSP ASIC prototyping environment.     

Using FPGAs to implement self-timed systems

Asynchronous or self-timed systems that do not rely on a global clock to keep system components synchronized can offer significant advantages over traditional clocked circuits in a variety of applications. In order to ease the complexity of this style of design, however, suitable self-timed circuit primitives must be available to the system designer. This article describes a technique for building self-timed circuits and systems using a library of circuit primitives implemented using Actel field programmable gate arrays (FPGAs). The library modules use a two-phase transition signaling protocol for control signals and a bundled protocol for data signals. A first-in first-out (FIFO) buffer and a simple routing chip are presented as examples of building self-timed circuits using FPGAs.This work was supported in part by NSF award MIP-9111793.     

A Predictably Low-Leakage ASIC Design Style

In this paper, we describe a new low-leakage standard cell based application-specific integrated circuit (ASIC) design methodology. This design is based on the use of modified standard cells, designed to reduce leakage currents (by almost two orders of magnitude) in standby mode and also allow precise estimation of leakage current. For each cell in a standard cell library, two low-leakage variants of the cell are designed. If the inputs of a cell during the standby mode of operation are such that the output has a high value, we minimize the leakage in the pull-down network, and similarly we minimize leakage in the pull-up network if the output has a low value. In this manner, two low-leakage variants of each standard cell are obtained. While technology mapping a circuit, we determine the particular variant to utilize in each instance, so as to minimize leakage of the final mapped design. We have performed experiments to compare placed-and-routed area, leakage and delays of this new methodology against Multithreshold CMOS (MTCMOS) and a regular standard cell based design style. The results show that our new methodology (which we call the "HL" methodology) has better speed and area characteristics than MTCMOS implementations. The leakage current for HL designs can be dramatically lower than the worst-case leakage of MTCMOS based designs, and two orders of magnitude lower than the leakage of traditional standard cells. An ASIC design implemented in MTCMOS would require the use of separate power and ground supplies for latches and combinational logic, while our methodology does away with such a requirement. Another advantage of our methodology is that the leakage is precisely estimable, in contrast with MTCMOS. Our primary contribution in this paper is a new low leakage design style for static CMOS designs. In addition, we also discuss techniques to reduce leakage in dynamic (domino logic) designs     

Modeling, Quantitative Analysis, and Design of Switched-Current Pipeline A/D Converters

Switched-current (SI) analog-to-digital converters (ADCs) are desirable for biomedical applications. Until now, SI ADCs are lacking effective and systematic computer-aided analysis and design (CAD) tools, particularly for noise. In this paper, models for different SI multiplying-digital-to-analog-converter (MDAC) designs are analytically derived, with the inclusion of distortion and noise. The models can be further programmed into an equation-based SI analog CAD tool. In this paper, the equation-based models (EBMs) are used to quantitatively analyze SI MDACs. Simulation results show that noise significantly limit the performance of SI MDACs. Optimal performance boundaries are derived for single-ended and fully differential SI MDACs. The boundaries from EBMs are consistent with the published SI circuit measurements. A methodology is formulated to design efficient SI MDACs. The EBM and the design methodology are further verified by designs of two sample SI MDACs in an AMS 0.35-mum CMOS process with SPICE simulation. Results from the EBM match those from real circuit models well, except for the noise of SI MDACs with feedback, in which case, the design margin should be added to the target performance. For low-/medium-resolution (<12 bit) applications, a pipeline ADC with a simple SI MDAC is the most efficient. Nonetheless, single-ended SI ADCs are susceptible to source noise. For high-resolution applications, only fully differential SI pipeline ADCs can be selected.     

Design of high-speed two-stage cascode-compensated operational amplifiers based on settling time and open-loop parameters

Settling behavior of operational amplifiers is of great importance in many applications. In this paper, an efficient methodology for the design of high-speed two-stage operational amplifiers based on settling time is proposed. Concerning the application of the operational amplifier, it specifies proper open-loop circuit parameters to obtain the desired settling time and closed-loop stability. As the effect of transfer function zeros has been taken into account, the proposed methodology becomes more accurate in achieving the desired specifications. Simulation results are presented to show the effectiveness of the methodology.     

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture

Novel circuits and design methodology of the massively parallel processor based on the matrix architecture are introduced. A fine-grained processing elements (PE) circuit for high-throughput MAC operations based on the Booth's algorithm enhances the performance of a 16-bit fixed-point signed MAC, which operates up to 30.0GOPS/W. The dedicated I/O interface circuits are designed for converting the direction of data access and supporting the interleaved memory architecture, and they are implemented for maximizing the processor core efficiency. Power management techniques for suppressing current peaks and reducing average power consumption are proposed to enhance the robustness of the macro. The circuits and the design methodology proposal in this paper are attractive for achieving a high performance and robust massively parallel SIMD processor core employed in multimedia SoCs     

Floating-Point Divider Design for FPGAs

Growth in floating-point applications for field-programmable gate arrays (FPGAs) has made it critical to optimize floating-point units for FPGA technology. The divider is of particular interest because the design space is large and divider usage in applications varies widely. Obtaining the right balance between clock speed, latency, throughput, and area in FPGAs can be challenging. The designs presented here cover a range of performance, throughput, and area constraints. On a Xilinx Virtex4-11 FPGA, the range includes 250-MHz IEEE compliant double precision divides that are fully pipelined to 187-MHz iterative cores. Similarly, area requirements range from 4100 slices down to a mere 334 slices     

嵌入式SATA2.0接口控制器中的非对称缓冲器设计

本文描述了基于Xilinx Virtex-5FPGA的嵌入式SATA2.0主机接口控制器中,物理层与链路层之间数据位宽转换缓冲器的设计方法.针对转换过程中可能会出现的数据错序问题,采用多比特移位寄存器组设计了应用于物理层16bit与链路层32bit位宽数据之间的转换电路.仿真和板级验证结果表明,该逻辑电路与Xilinx FPGA内嵌的FIFO相比,平均时延降低了70%,在完成相同功能的情况下,使用了更少的芯片资源和控制逻辑.     

Hardware/Software Design Considerations for Automotive Embedded Systems

An increasing number of safety-critical functions is taken over by embedded systems in today's automobiles. While standard microcontrollers are the dominant hardware platform in these systems, the decreasing costs of new devices as field programmable gate arrays (FPGAs) make it interesting to consider them for automotive applications. In this paper, a comparison of microcontrollers and FPGAs with respect to safety and reliability properties is presented. For this comparison, hardware fault handling was considered as well as software fault handling. Own empirical evaluations in the area of software fault handling identified advantages of FPGAs with respect to the encapsulation of real-time functions. On the other hand, several dependent failures were detected in versions developed independently on microcontrollers and FPGAs.