Analysis of reliability and optimization of ESD protection devices supported by modeling and simulation

An analysis of electrostatic discharge (ESD) protection structures supported by advanced 2-D mixed mode electro-thermal device and circuit simulation with calibrated electro-physical models to increase the reliability of protected IC’s is presented. The critical temperature as a criterion of device destruction is defined and experimentally verified. Numerical simulation and visualization of the internal electro-physical properties of the analyzed structures during a very short ESD pulse considerably improved the understanding of their physical behavior and contributes to a proper design and optimization of doping and geometry of the analyzed ESD protection devices. The analyzed devices are designed as protection against Human Body Model (HBM) and International Electromechanical Commission model (IEC) 61000-4-2 with very high robustness. The obtained results are shown on two examples. Modification of the device layout by splitting the cathode contact of the ESD diode into two parts allowing area reduction with improved electrical characteristics is the subject of the first example. The influence of doping fluctuations on the device robustness is presented in the second example. Different triggering and failure mechanisms of the diode and transistor structure during HBM and IEC pulse are presented.     

3D electro-thermal investigations for reliability of ultra low ON state resistance power MOSFET

This paper presents a methodology and tool based on 3D electro-thermal finite elements modeling intended to analyze the sequence of the events after emergence of defects in automotive power MOSFETs. Finite element modeling of power device and its nearby environment is detailed. The effects of delamination and bonding wire lift off on device transient electro-thermal behavior are investigated during a short circuit mode. Thus it helps to quantify the electro-thermal impact of the damages. Such modeling is useful for optimization of structure design to guarantee a longer lifespan.     

Evaluation of the ruggedness of power DMOS transistor from electro-thermal simulation of UIS behaviour

High-voltage power MOSFETs have been widely used in switching mode power supply circuits as output drivers for industrial and automotive electronic control systems. However, as the device size is reduced, the energy handling capability is becoming a very important issue to be addressed together with the trade-off between the series on-resistance R_ON and breakdown voltage V_BR. Unclamped inductive switching (UIS) condition represents the circuit switching operation for evaluating the “ruggedness”, which characterizes the device capability to handle high avalanche currents during the applied stress. In this paper we present an experimental method which modifies the standard UIS test and allows extraction of the maximum device temperature after the applied standard stress pulse vanishes. Corresponding analysis and non-destructive prediction of the ruggedness of power DMOSFETs devices supported by advanced 2-D mixed mode electro-thermal device and circuit simulation under UIS conditions using calibrated physical models is provided also. The results of numerical simulation are in a very good correlation with experimental characteristics and contribute to their physical interpretation by identification of the mechanism of heat generation and heat source location and continuous temperature extraction.     

A highly-compact packaging design for improving the thermal performance of multi-finger InGaP/GaAs collector-up HBTs

To satisfy the increasing demand for small power amplifiers in advanced cellular phones, we have investigated the thermal performance of multi-finger InGaP/GaAs collector-up HBTs with a heat-dissipation packaging configuration. The thermal interaction between collector fingers and the size effect on the maximum operation temperature within the transistor have been scrutinized. In addition, the thermal handling for a stable operation in the device has been optimized through the variation of finger pitches. The superior results show that the thickness of the heat-dissipation structure can be reduced by more than 35%, and the achieved thermal resistance can be effectively improved over 40%. Based on appropriate approaches from the 3-D numerical simulation for thickness-adjusting evaluation and the analytical analysis for finger-pitch optimization, a highly-compact packaging design is proposed for the miniaturization of collector-up HBTs in future mobile communication systems.     

Compact modelling and analysis of power-sharing unbalances in IGBT-modules used in traction applications

IGBT modules are critical components for the reliability of power converters used in traction applications. A thorough analysis of all stressful operating conditions is a complex task, which requires versatile simulation capability. In this paper a comprehensive electro-thermal model of an IGBT-module is developed. Then, circuit simulation is used to investigate the power sharing between parallel chips during transient operation. Unbalances are observed, their causes identified and their influence on device degradation pointed out and discussed.     

多栅指AlGaN/GaN HEMT器件自热效应研究

Self-heating in multi-finger AlGaN/GaN high-electron-mobility transistors(HEMTs) is investigated by measurements and modeling of device junction temperature under steady-state operation.Measurements are carried out using micro-Raman scattering to obtain the detailed and accurate temperature distribution of the device.The device peak temperature corresponds to the high field region at the drain side of gate edge.The channel temperature of the device is modeled using a combined electro-thermal model considering 2DEG transport characteristics and the Joule heating power distribution.The results reveal excellent correlation to the micro-Raman measurements, validating our model for the design of better cooled structures.Furthermore,the influence of layout design on the channel temperature of multi-finger AlGaN/GaN HEMTs is studied using the proposed electro-thermal model, allowing for device optimization.     

Thermoelectrical modelling and simulation of devices based on VO2

Limits of development of conventional silicon-based integrated circuits get closer. More and more effort is done to develop new devices for integrated circuits. A promising structure is based on the semiconductor-to-metal phase change of vanadium-dioxide at about 67 °C. In these circuits the information is carried by combined thermal and electrical currents. For device modelling and circuit design, accurate distributed electro-thermal transient simulation is mandatory. This paper is the first one to present an electro-thermal transient simulation method for VO₂ devices operating in real-world conditions. The paper presents three VO₂ material models, the algorithmic extension of an electro-thermal field simulator to be able to handle hysteresis and the transient simulation issues of VO₂ and the modelling of VO₂ based devices. The paper compares measured and simulated device characteristics.     

激光发射天线仿真平台设计

为了给激光发射天线的设计优化提供一种可视化自动设计手段，采用MATLAB仿真技术构建了一种基于倒置望远镜系统结构的激光发射天线仿真平台, 进行了激光发射天线的理论分析和仿真实验验证。通过灵活设置激光谐振腔关键结构参量以及倒置望远镜系统透镜组合方式，实现了发射天线发射前后的激光2维光强分布、激光3维光强分布、激光光束3维结构以及变换后激光束腰与透镜组合离焦量的关系曲线的仿真。结果表明，波长550nm的激光变换后束腰半径从0.073mm变为12.202mm，发散角从0.275°变为0.00164°，成功压缩了激光发散角; 此平台进行的仿真过程形象直观，可根据需要自动优化设计出最优的激光发射天线结构。该仿真平台的构建为激光发射天线的可视化自动设计提供了全新的方法。     

Analysis of multifinger power HEMTs supported by effective 3-D device electrothermal simulation

The influence of the metallization layer geometry on the electrothermal behavior of the multifinger power high-electron mobility transistors (HEMTs) is studied. The analysis of thermal and electrical behavior is supported by effective 3-D electrothermal device simulation method developed for Synopsys TCAD Sentaurus environment using mixed-mode setup. The proposed methodology allows fast simulation of complex systems from individual semiconductor layers at a frontend up to package and cooling assemblies at a backend. More accurate electrothermal model of power HEMT is proposed and validated by finite element method (FEM) simulations. The analysis points on significant influence of metallization geometry design on electrothermal properties and reliability of the multifinger power HEMTs. The unique identification and visualization of the critical regions allows effective device optimization. Very good comparison between simulation results and experimental data demonstrate validity of the proposed simulation methodology and HEMT structures analysis.     

A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations

This paper presents a forward body-biasing (FBB) technique for active and standby leakage power reduction in cache memories. Unlike previous low-leakage SRAM approaches, we include device level optimization into the design. We utilize super high Vt (threshold voltage) devices to suppress the cache leakage power, while dynamically FBB only the selected SRAM cells for fast operation. In order to build a super high Vt device, the two-dimensional (2-D) halo doping profile was optimized considering various nanoscale leakage mechanisms. The transition latency and energy overhead associated with FBB was minimized by waking up the SRAM cells ahead of the access and exploiting the general cache access pattern. The combined device-circuit-architecture level techniques offer 64% total leakage reduction and 7.3% improvement in bit line delay compared to a previous state-of-the-art low-leakage SRAM technique. Static noise margin of the proposed SRAM cell is comparable to conventional SRAM cells.     

Electro-Thermally Coupled Power Optimization for Future Transistors and Its Applications

We report a novel electro-thermally coupled power-optimization methodology for future transistors. The methodology self-consistently yields the globally optimized total power and the corresponding temperature as a function of delay for a given set of transistors (bulk, double-gate FET, fully depleted SOI, and partially depleted SOI) at future technology nodes. When SPICE models are not necessarily available and simple device models are highly inadequate because of complex 2D device effects, these derived power/temperature versus delay curves serve as a comprehensive standard to compare any two transistors for future technology-node device selections. Because the power optimization is global (over various transistor parameters and includes leakage as well as dynamic power) and is self-consistently coupled to electro-thermal models, the methodology provides the optimum operational supply voltage (V_dd) and the device parameters (body thickness, equivalent oxide thickness, and gate metal work function) for future transistors targeting 45-nm technology node. Furthermore, it can be used to provide insight into advance nodes, device-specific hot-spot problems, multiple V_t, V_dd design for different functional blocks, transistor design, and evaluating the efficacy of novel thermal solutions such as superior thermal conductivity and subambient cooling.     

Design considerations of power MOSFET for high frequencysynchronous rectification

Synchronous rectifiers used in high frequency, low output voltage applications are power MOSFETs specially designed to replace the usual output Schottky diodes in order to reduce converter losses. This paper deals with the analysis and design optimization of a synchronous rectifier suitable for applications of 1 to 10 MHz switching-mode power supplies. Three different MOSFET structures were studied and evaluated through detailed 2-dimensional device simulations. The internal parameters are optimized against three major performance factors, namely (1) the recovery time of the body diode, (2) the product of on-state resistance and input capacitance, i.e., the loss factor, and (3) the breakdown voltage of the body diode. Based on the evaluation, the UMOS structure produces the lowest RC loss factor and the shortest body diode reverse recovery. The final design optimization of the UMOS was then carried out and an optimized device is presented as the final design     

A design tool to study the impact of mission-profile on the reliability of SiC-based PV-inverter devices

This paper introduces a reliability-oriented design tool for a new generation of grid connected PV-inverters. The proposed design tool consists of a real field mission profile model (for one year operation in USA-Arizona), a PV-panel model, a grid connected PV-inverter model, an electro-thermal model and the lifetime model of the power semiconductor devices. A simulation model able to consider one year real field operation conditions (solar irradiance and ambient temperature) is developed. Thus, one year estimation of the converter devices thermal loading distribution is achieved and is further used as an input to a lifetime model. The proposed reliability oriented design tool is used to study the impact of MP and device degradation (aging) in the PV-inverter lifetime. The obtained results indicate that the MP of the field where the PV-inverter is operating has an important impact in the converter lifetime expectation, and it should be considered in the design stage to better optimize the converter design margin. In order to improve the accuracy of the lifetime estimation it is crucial to consider also the device degradation feedback (in the simulation model) which has an impact of 30% in the precision of the lifetime estimation in the studied case.     

高频高压电源中倍压器的设计

倍压器作为高压电源的重要组成部分对于提高电源的性能具有特殊作用。分析了倍压器相关参数对电源性能的影响规律,用理论分析的方法设计了一种半臂式倍压器,并对其进行了实际测试。仿真与测试结果表明,倍压器参数优化对于电源性能具有显著影响,且实现了倍压器设计的优化。     

Structure optimization of polymeric Mach-Zehnder rib waveguide

The polymeric material is very promising for fabricating the integrated optical waveguide devices. The polymeric op- tical waveguide has become the hotspot because the poly- meric material can offer a series of merits, such as easy integration, rapid resp…     

Improved thermal management of low voltage power devices with optimized bond wire positions

This paper focuses on optimization of bond wire positions as a method to improve thermal management of power semiconductors. For this purpose, robustness of a new low-voltage MOSFET generation with an optimized multiple bond wire arrangement and device shape is compared to an older device design with lower number of bond wires. 2D electrical simulation is used to evaluate the lateral distribution of power dissipation due to the gate voltage de-biasing effect. 3D thermal finite element simulation and infrared thermography measurements are employed to analyze the corresponding surface temperature distribution. Finally, tests under extreme single pulse short-circuit conditions demonstrate the effectiveness of thermal management for improving robustness in automotive applications.     

Modeling and Design of RF Amplifiers for Envelope Tracking WCDMA Base-Station Applications

Wideband code division multiple access (WCDMA) base-station RF amplifiers using a variety of device technologies including GaN field-effect transistors (FETs), Si LDMOS, and GaAs high-voltage heterojunction bipolar transistors (HVHBTs) are modeled, optimized, and compared for use in wideband envelope tracking (ET) system. A quasi-static approach is employed to effectively model the supply-modulated RF amplifiers, and thus facilitate the design optimization process. A new design methodology for ET RF amplifiers is introduced including identification of optimum fundamental and harmonic terminations. The fundamental and harmonic impedances have been successfully optimized for various RF devices and good agreement has been achieved between the simulation and measurement results. Among the modeled and measured ET RF amplifiers, a GaAs HVHBT exhibits the best overall efficiency of 60% with an average output power of 33 W and a gain of 10 dB for a WCDMA signal with 3.84-MHz bandwidth and 7.7-dB peak-to-average power ratio, while meeting all linearity requirements of the WCDMA standard. Desirable device characteristics for optimum ET operation are also discussed.     

An integrated technology CAD system for process and devicedesigners

A workstation-based integrated system with a highly interactive X/Motif user interface is discussed. At present, TSUPREM3, TSUPREM4 and TPISCES have been integrated into this system. The components of the integrated TCAD system include a generic process recipe editor, a mask editor, a 2-D wafer structure builder (using 1-D/2-D process simulation profiles), a mesh generator for 2-D device simulation, a device simulation recipe editor, and graphical postprocessors for both process and device analysis. The user of this system inputs the specification of a process recipe and the layout of the device structure to be fabricated. The system then runs process and device simulation using incremental and shared simulation strategies to generate wafer structure and electrical device characteristics. An interactive user interface guides the user through the process and device simulation flow. thereby aiding what-if analysis of process and device tradeoffs     

GaAs基改性高电子迁移率晶体管(MHEMT)的计算机模拟与优化

讨论了针对GaAs基改性高电子迁移率晶体管(MHEMT)的异质层结构参数的设计优化方法,详细给出了有关的设计步骤与公式。在数值分析与比较的基础上,并综合考虑材料生长与器件工艺的简便性,得到一组优化的MHEMT异质层结构设计参数。模拟所得的器件DC与RF特性充分显示其在功率与低噪声应用上的巨大潜力。验证性的1μm×200μmMHEMT取得的fT=30GHz、fmax=170GHz的结果佐证了理论分析的正确性。     

On the extraction of PiN diode design parameters for validation of integrated power converter design

Design of integrated power systems requires prototype-less approaches. Accurate simulations are necessary for analysis and verification purposes. Simulation relies on component models and associated parameters. The paper focuses on a step-by-step extraction procedure for the design parameters of a one-dimensional finite-element-method (FEM) model of the PiN diode. The design parameters are also available for diverse physics-based analytical models. The PiN diode remains a complex device to model particularly during switching transients. The paper demonstrates that a simple FEM model may be considered unknowingly of the device exact technology. Heterogeneous simulation is illustrated. The state-of-art of parameter extraction methods is briefly recalled. The proposed procedure is detailed. The diode model and extracted parameters are systematically validated from electro-thermal point-of-view. Validity domains are discussed.