基于MAC单元的低功耗低延时FIR滤波器的设计与分析

乘法器在数字信号处理系统中承担了很重要的作用,而乘法器消耗相当大的功耗,因此有必要进行乘法器的低功耗研究。介绍一种基于乘法累加(MAC)单元的FIR滤波器的设计,其中乘法器利用基4华莱士树乘法器,加法器利用超前进位加法器,在优化整合之后,得到低延时低功耗FIR滤波器。实验证明,该文设计的FIR滤波器具有很小的延时与很低的动态功耗。     

基于可重构FPGA技术的自适应FIR滤波器的实现

有限冲激响应(FIR)滤波器设计遇到的难题是滤波要进行大量乘法运算,即使是在全定制的专用集成电路中也会导致过大的面积与功耗.对于用硬件实现系数是常量的专用滤波器,可以通过分解系数变为应用加、减和移位而实现乘法.FIR滤波器的复杂性主要由用于系数乘法的加法器/减法器的数量决定.而对于自适应FIR滤波器,大多数场合下可用数字信号处理器(DSP)或CPU通过软件编程的方法来实现,但是对于要求高速运算的场合,VLSI实现是很好的选择.基于这一考虑,可以用符号数的正则表示(CSD)码表示系数, 再利用可重构现场可编程门阵列(FPGA)技术实现.可重构结构的应用,能保证系统的其余部分同时处于运行状态时实现FIR滤波器系数的更新.文中利用CSD码和可重构思想,提出了用FPGA实现自适应FIR滤波器的一种方案.     

基于亮度补偿算法的显示子系统低功耗的设计

低功耗设计是嵌入式系统的一个重要课题,显示系统的功耗在整个系统功耗占有很大比例,降低显示系统功耗成为嵌入式低功耗设计的重中之重。设计基于WindowsMobile操作系统、PXA270处理器,以标准亮度补偿算法为基础,动态降低背光电流以节省功耗,同时相应的调整LCD屏的光透过率,以补偿背光亮度降低带来的图像亮度降低,在人眼可接受的失真范围内,实现了系统功耗的降低。整个设计在驱动层实现,功能稳定,有很好的可移植性。     

基于循环缓冲区FIR滤波器的设计

数字滤波技术主要包括滤波器设计及滤波过程的实现两方面内容。文中阐述了FIR滤波器基本结构,结合实例用Matlab来确定FIR滤波器系数,分析了循环缓冲区算法原理。在该算法的基础上,结合设计的滤波器实现对输入混合信号的FIR数字滤波,最后给出了滤波前后输入输出信号波形仿真。     

FIR带通滤波器的FPGA实现

为设计一个项目可用的FIR数字带通滤波器,采用Matlab/Simulink软件中DSPBulider强大的算法模块设计工具,结合Altera公司的FPGA开发板实现FIR数字带通滤波器的系统集成、RTL级仿真、综合编译、下载等设计流程,并对正弦信号进行滤波,结果下载到开发板上用示波器观测,达到了预期的滤波效果和目的.基于DSPBuilder完成系统建模,省去了复杂的VHDL编程,还可针对具体模块进行参数设置从而适应不同的滤波需求.该方法实现简单、可靠,还可类推实现其他复杂的嵌入式系统设计.     

E-band通信系统中高速并行FIR成形滤波器设计

为实现E-band(E频段)通信系统中的高速成形滤波,在已有快速FIR滤波算法(FFA)基础上,通过快速短卷积迭代以及张量展开算法,设计了一种高速并行FIR成形滤波器,并进行硬件复杂度分析与时延分析。浮点和定点数仿真验证结果表明,所设计高速并行滤波器在硬件实现上可减少21%的乘法运算操作和1314%的时延单元,6比特以上小数量化可达到系统成形滤波需求。     

一种超低功耗小面积的Σ-Δ ADC数字抽取滤波器

提出并实现了一种针对音频信号Σ-Δ模数转换器的超低功耗和低资源占用的数字抽取滤波器。该滤波器采用多级级联结构,由级联积分梳状滤波器、极简结构补偿器和全通多相型IIR滤波器组成,相较于传统FIR滤波器级联方案,能够以极低的阶数和硬件复杂度实现高倍抽取、极小的通带波纹和高水平的阻带衰减,同时具有近似线性相位特性。整体有效带宽为20 kHz,共完成128倍抽取。采用0.18 μm CMOS工艺完成ASIC设计,数字版图面积为0.37 mm²,功耗为125 μW,信噪比达到98.79 dB,有效位数为16 bit。与传统FIR结构抽取滤波器相比, 面积减小了60%, 功耗降低了20%。     

一种低复杂度的稀疏FIR陷波滤波器的设计方法

FIR陷波滤波器具有线性相位、精度高、稳定性好等诸多优势,然而当陷波性能要求较高时,通常需要较高的阶数,导致FIR陷波滤波器硬件实现复杂度大大提高。该文基于稀疏FIR滤波器设计算法和共同子式消除的思想,提出一种低复杂度的FIR陷波滤波器设计方法。该方法首先采用稀疏滤波器设计算法得到满足频域性能设计要求的FIR陷波原始滤波器系数,然后对其进行CSD编码,并分析CSD编码量化系数集中所有的2项子式和孤子的灵敏度,最后根据灵敏度的大小依次选择合理的2项子式或孤子直接合成滤波器系数集。仿真结果表明,新算法设计实现的FIR陷波滤波器比已有的低复杂度设计方法最多可减少51%的加法器,有效地降低了硬件实现复杂度,大大节省了硬件资源。     

基于嵌入式处理器的系统级低功耗管理研究

针对嵌入式系统低功耗设计问题,分析了动态功率管理DPM和动态电压/频率调节DVFS两种嵌入式功耗管理策略,并提出了系统级低功耗控制框架.讨论了基于嵌入式处理器i.MX1硬件平台实现系统级功耗控制方案,并给出了具体的设计方法.实际应用表明,该设计方案可有效降低系统能耗.     

4模剩余数系统FIR数字滤波器设计

基于四模余数系统的FIR滤波器将一个滤波系统分为4个彼此独立,互不影响,并行运算的子滤波通道,消除了各个子运算通道之间的进位链,加快了计算的速度,提高了滤波精度。所有模都具有2n 和2n±1的形式,电路完全基于组合逻辑电路来实现。结果表明,无论在功耗,速度,实现复杂度等方面,采用余数系统构建的FIR滤波器都优于于传统二进制FIR滤波器。     

Adaptive low-power address encoding techniques using self-organizing lists

Off-chip bus transitions are a major source of power dissipation for embedded systems. In this paper, new adaptive encoding schemes are proposed that significantly reduce transition activity on data and multiplexed address buses. These adaptive techniques are based on self-organizing lists to achieve reduction in transition activity by exploiting the spatial and temporal locality of the addresses. Also the proposed techniques do not require any extra bit lines and have minimal delay overhead. The techniques are evaluated for efficiency using a wide variety of application programs including SPEC 95 benchmark set. Unlike previous approaches that focus on instruction address buses, experiments demonstrate significant reduction in transition activity of up to 54% in data address buses and up to 59% in multiplexed address buses. The average reductions are twice those obtained using current schemes on a data address bus and more than twice those obtained on a multiplexed address bus.     

面向CAN总线健壮性的形式化建模与验证

为评估控制器局域网络（Controller Area Network,CAN）攻击者入侵风险的影响,增强CAN总线设计的健壮性,提出了一种基于UPPAAL SMC的CAN总线健壮性验证方案。该方案首先针对嵌入式软件系统需求对CAN总线数据链路层与应用层进行形式化建模,采用模型检测技术对总线控制、收发、仲裁、应用层等功能进行仿真;其次使用攻击报文对CAN总线系统抗攻击性能进行验证与分析,开发人员可根据验证结果改进软件需求参数指标。实验结果表明,参数优化后,在总线被攻击情况下节点传输的准确率保持在75%以上,应答正确率可提升12.4%,加强了总线抗攻击能力。该方法为嵌入式软件通信总线系统设计的合理性提供了理论指导,规避开发后期的风险,可广泛应用于通信总线安全性能验证领域。     

一种基于频繁值和位变换感知的数据总线节能方法

深亚微米工艺下,片上数据总线能耗占嵌入式多核芯片能耗的比重越来越大.FV-MSB（Frequent Value-Most Significant Bits）方法降低了片外数据总线的能耗,但对于非频繁值和频繁高位值的低位部分未做处理,为进一步降低片上总线动态能耗,设计了一种基于频繁值和位变换感知的片上总线节能方法.利用频繁值和对位变换数的感知选择编码方式,大幅减少了数据总线上的位变换,有效降低了总线动态能耗.70nm工艺下,仿真实验结果显示,本文的方法最大节能比例可达17.76%,平均节能比例达16.91%,较FV-MSB方法使节能比例提高了6.28%.并且节能比例随λ的变化趋势表明本方法在未来工艺尺寸缩小时仍能发挥作用.     

I2C总线驱动在嵌入式系统中的两种实现

I2C总线是一种用于IC器件之间连接的二线制总线,在嵌入式系统中有广泛的应用。嵌入式处理器本身携带I2C控制器时,可以直接通过配置特殊寄存器来实现I2C的功能;而当缺少I2C控制器时,则需要通过软件模拟的方法来实现。简要地叙述了I2C总线协议及其时序,并给出了I2C总线驱动在ARM S3C4510处理器下的两种实现方法,最后以模拟的实现方式给出一个应用实例。     

基于FPGA的动态分布式算法的研究与应用

为了提高FPGA对乘积和运算的处理速度和灵活性,在分布式运算法的基础上,采用动态查询表代替ROM,提出了一种占用硬件资源少、运算速度快、系数可在线编程的动态分布式乘积和运算算法。该算法不仅摆脱了固定数据总线宽度和运算顺序执行对数字信号处理速度的限制,同时为实现系数可编程FIR滤波器提供了有效的解决方案。     

Estimating data bus size for custom processors in embedded systems

We propose a method to estimate the data bus width to the requirements of an application that is to run on a custom processor. The proposed estimation method is a simulation-based tool that uses Extreme Value Theory to estimate the width of an off-chip or on-chip data bus based on the characteristics of the application. It finds the minimum number of bus lines needed for the bus connecting the custom processor to other units so that the probability of a multicycle data transfer on the bus is extremely unlikely. The potential target platforms include embedded systems where a custom processor (i.e. an ASIC or a FPGA) in a system-on-a-chip or a system-on-a-board is connected to memory, I/O and other processors through a shared bus or through point-to-point links. Our experimental and analytical results show that our estimation method can reduce the data bus width and cost by up to 66% with an average of 38% for nine benchmarks. The narrower data bus allows us to increase the spacing between the bus lines using the silicon area freed from the eliminated bus lines. This reduces interwire capacitance, which in turn leads to a significant reduction of bus energy consumption. Bus energy can potentially be reduced up to 89% for on-chip data buses with an average of 74% for seven benchmarks. Also, reduction in the interwire capacitance improves the bus propagation delay and on-chip bus propagation delay can be reduced up to 68% with an average of 51% for seven benchmarks using a narrower custom data bus.     

基于国产SoPC平台的外部总线的设计与实现

可重构的SoC(system-on-a-chip)是嵌入式系统发展的一个重要方向,它不仅可以达到较高的性能而且更加的灵活.介绍了一种国产的SoPC(System on a Programmable Chip)平台,并基于此平台提出了一种用于重构计算的外部总线结构.通过该总线,可以通过改变不同的IP(intellectual property)核来组成新的系统.同时回顾总结了部分动态可重构的步骤并完成了一个完整的系统,最后给出了可重构系统的测试结果.     

Low-power instruction bus encoding for embedded processors

This paper presents a low-power encoding framework for embedded processor instruction buses. The encoder is capable of adjusting its encoding not only to suit applications but furthermore to suit different aspects of particular program execution. It achieves this by exploiting application-specific knowledge regarding program hot-spots, and thus identifies efficient instruction transformations so as to minimize the bit transitions on the instruction bus lines. Not only is the switching activity on the individual bus lines considered but so is the coupling activity across adjacent bus lines, a foremost contributor to the total power dissipation in the case of nanometer technologies. Low-power codes are utilized in a reprogrammable application specific manner. The restriction to two well-selected classes of simply computable, functional transformations delivers significant storage benefits and ease of reprogrammability, in the process obtaining significant power savings. The microarchitectural support enables reprogrammability of the encoding transformations in order to track code particularities effectively. Such reprogrammability is achieved by utilizing small tables that store relevant application information. The few transformations that result in optimal power reductions for each application hot-spot are selected by utilizing short indices stored into a table, which is accessed only once at the beginning of the transformed bit sequence. Extensive experimental results show significant power reductions ranging up to 80% for switching activity on bus lines and up to 70% when bus coupling effects are also considered.     

A switched memory decoding circuit for bus oriented microprocessor systems

Switched memory decoding can be of considerable practical use in the development of microprocessor systems, particularly embedded microprocessor systems, in situations when prototypes for evaluation are required at an early stage. In the case of bus oriented microprocessor systems, a switched memory decoding module can be conveniently designed on a single printed circuit, which can be plugged into the bus during development and prototype evaluation, and then replaced by a permanent memory in the final unit. In this paper the design of a switched memory decoding circuit is described, which can be used in bus oriented microprocessor systems equipped with the MC6800 MPU.     

Wrapper-based bus implementation techniques for performance improvement and cost reduction

A low-cost wrapper-based bus implementation is described that performs well in system-on-chip (SOC) designs. Novel wrapper implementation techniques are used to create wrappers without embedded data buffers. The bus uses 1) a novel slave wrapper interface that supports flow control signals, 2) a write buffer switching technique for the master wrappers to achieve good performance at a small hardware cost, 3) a novel retry management technique called slave designated retry control (SDRC) to enable slow IP core connections and a livelock avoidance scheme using the SDRC technique, and 4) a novel bit-width conversion technique using data-width converters embedded in the bus multiplexers. A CPU-based SOC designed with the proposed bus showed that these techniques can increase throughput by about 14%, and reduce read and write latencies by about 16% and 11% compared to a conventional wrapper-based bus, when running a modeled average traffic pattern for this chip. The implemented results show that these techniques can reduce the hardware costs by 28% or 50% compared with two conventional wrapper-based conversion techniques. The chip is implemented using 0.15-/spl mu/m CMOS process technologies. The area for the on-chip bus is 3.3 mm/sup 2/ and the operation clock frequency is 200 MHz.