步进升温恒温箱温度的高精度分段检测器

介绍一种能准确跟踪测量高稳定步进升温恒温箱温度的高精度检测器的设计。此检测器采用两种热敏元件分段工作，有效地克服了单种温度传感器难以同时满足线性范围宽和分辨能力强的缺点，在恒温箱步进升温过渡段，其分辨率为０．１℃；在温度稳定段，其分辨率为０．０１℃。     

基于单片机的炭黑复合导电材料的电阻-温度测量系统

以AT89S51单片机为核心,采用热电偶放大器芯片AD595,设计炭黑复合导电材料的电阻-温度测试系统,实现了电阻和温度的测量.介绍系统的硬件结构和软件设计方法,特别是温度和电阻的采集和显示过程.实验结果表明,设计的系统能够方便准确地测量电阻和温度的变化,测量数据验证了炭黑复合导电材料的PTC特性.     

SL系列集成温度探头原理及应用

本文所介绍的集成温度探头是近年来迅速发展起来的一种新颖温敏组件,具有线性优良、性能稳定、灵敏度高、无需补偿、热容量小、输出信号大、使用方便等特点。在薄小型化、功能、性能及能耗等方面都比传统温度传感器(如热电阻、半导体热敏电阻、白金测温电阻、热电偶等)要好。可广泛用于各种冰箱、空调机、恒     

温度及电压精密测量仪表

National Instruments宣布推出新的精密插件板系列。这是特别为以热电偶、电阻式温度检测器、热敏电阻器测温而精心设计的。这种DAQMeter4350系列插件板的特点,是能够进行5(1/2)位测量精度和采用低噪声设计,在以高精度热电偶、电阻式温度检测器、热敏电阻器等进行测量时,能保证精确的电流激励。此外,它的输入范围是±15V,所以也能测量其他低带宽的模拟信号。 DAQMeter4350系列插件板包括了     

一种判断氧化物阴极活性的简便方法

用降落法测量氧化物阴极活性时，常常要测量其特征温度。本文叙述了一种供生产使用的测量氧化物阴极特征温度的简便方法－电阻法（ＲＭ）；该方法的线路设计简单，操作简便，测量迅速，结果显示直观，对批量产品可进行测量。     

差动放大器构成精密电流源的核心

许多应用利用精密电流源提供恒定电流,包括工业过程控制、仪器仪表、医疗设备和消费电子产品。例如,过程控制系统利用电流源提供电阻温度检测器（RTD）所需的激励电流; 数字万用表利用电流源测量未知电阻、电容和二极管; 长距离信息、传输广泛使用电流源来驱动4mA至20mA电流环路。     

正温度系数热敏电阻（PTCR）特性参数快速测试仪

本文介绍了一种快速测量正温度系数热敏电阻（ＰＴＣＲ）的重要参数（居里温度Ｔｃ和电阻温度系数αｔ）的测量方法，并根据这种方法设计了ＰＴＣＲ特性参数Ｔｃ，αｔ快速测试仪，该仪器的使用改变了传统测试方法时间长，工作量大的状况。通过测量ＰＴＣＲ在室温和两个特征温度下的电阻值，该仪器能很快计算并显示出Ｔｃ和αｔ的结果，大大提高了测试效率，该仪器以８０３１单片机系统为核心，简单实用，使用方便，成本低，文中介绍     

基于虚拟仪器的温度测量系统

基于虚拟仪器技术,利用热电偶设计了一套温度测量系统,包括硬件和软件设计,硬件包括对热电偶输出信号的放大和滤波,以及对冷端温度的补偿电路,冷端温度通过Pt100热电阻进行测量;软件采用Labview进行编写,界面简洁,可通过图形化的界面对温度进行实时监测。     

硅正电阻温度系数热敏电阻器

为获得一种在常温下具有正温特性的热敏电阻,采用硅单晶材料,利用其迁移率随温度变化的规律设计并制成了硅正电阻温度系数热敏电阻器。测量表明,其电阻值随温度升高而增大。温度系数为(0.6％～0.8％)℃~(-1),在-50～+100℃温度范围内具有准线性。硅正电阻温度系数热敏电阻器特别适合于各种半导体器件和传感器的温度补偿。     

高温区Hg1—xCdTe光导器件的温度—电阻关系

在２００～３００Ｋ范围内测量了ｎ－ＨｇＣｄＴｅ的电学参数，并推导了载流子浓度，迁移率，电阻和组分的关系表达式，所得结果与红外光谱测量数据符合，利用ＨｇＣｄＴｅ光导器件的电阻－温度特性确定组分，不需要电阻的精确值，是一种判断器件均匀性和性能的有效方法。     

一款切合实际的30A能量计

本文介绍了一款集成了30A检测电阻器LTC2947.     

A Nyquist-rate delta-sigma A/D converter

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require oversampling. Using this prototype, the design issues of the parallel delta-sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is verified. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to nonideal circuit behavior characteristic of the individual delta-sigma modulators     

A charge-domain D/A conversion system

In this article, a new multiplication type D/A conversion system using CCD is proposed and the result of simulations for evaluating its performance is reported. The system consists of a recursive charge divider which divides input charge-packet Qin sequentially into output charge-packets Qin · 2^-i and two charge-packet accumulators which accumulates output charge-packets from the recursive divider selectively according to digital input signal bits starting from MSB. The system converts input digital signal bit by bit, fully in charge-domain, thus the power consumption for this system is supposed to be very low. Also in this article, an effective method to achieve higher accuracy for splitting a charge-packet into two equal-sized packets using very simple hard-ware structure is proposed. As the result of simulations, we have found that the upper limit of accuracy for the conversion is determined by transfer efficiency of CCD, and within this range a trade-off relationship exists among conversion-accuracy, circuit-size and conversion-rate. This unique relationship enables to reduce the circuit size of D/A converter significantly maintaining the accuracy of conversion by slowing down the conversion-rate. This D/A converter is appropriate especially for the system integration because of its simple structure, tolerance to the fabrication error and low power consumption inherrent in the nature of CCD. By using of this system, it is expected to be possible to realize a focal plane image processor performing parallel analog operations such as DCT conversion with CCD imager incorporated on the same Si chip by the same MOS process technology.     

A monolithic video A/D converter

The design and measured performance of a fully parallel monolithic 8-bit A/D converter is reported. The required comparators and combining logic were designed and fabricated with a standard high-performance triple-diffused technology. A bipolar comparator circuit giving good performance with high input impedance is described. Circuit operation is reported at sample rates up to 30 megasamples per second (MS/s), with analog input signal power at frequencies up to 6 MHz. Full 8-bit linearity was achieved. An SNR of 42-44 dB was observed at input signal frequencies up to 5.3 MHz.     

一种识别说话者的新方法

在能够自动识别视频中的说话者的系统中,大部分采用的是声音和唇部运动相结合的方法。文中则采用了另一种方法有效地达到了目的,即通过检测人体头部和手部的运动来鉴别说话者。基于演讲者在说话时通常会伴有头部运动或是手部运动,该方法既能实现说话者的检测,又能避免由于观测点过远而导致无法判断人唇部运动的局限性。在系统的实施过程中,运用了多种图像处理方法,并且对三帧差运动法做出了改善,使其能更高效、更准确地检测到头部和手部的运动。经过多个不同的视频测试后,本系统的F1 score高达91．91％,从而验证了该系统的可行性。     

A charge-balancing monolithic A/D converter

The quest for a minimum-parts-count DPM led to the development of this monolithic, low power analog-to-digital converter. It incorporates the analog and digital functions historically implemented separately with specialized process technologies into a chip with full /spl plusmn/3 digit accuracy. The integration of resistors, compensation capacitors, and an oscillator reduces the external component complement to three capacitors and one adjustable reference. TTL compatible outputs include sign, overrange, and under range information in addition to the three digit strobes and the BCD data outputs. The logic operates between +5 V and ground, the linear section between +5 V and -5 V. The paper describes the conversion algorithm and its CMOS implementation, emphasizing the analog design of this innovative device.     

A Convenient Multivariate Gram-Charlier Type A Series

It is often necessary to approximate the probability density function of a random variable from given statistical moments. The Gram-Charlier Type A series is one well known method for such representations. In this note, the Gram-Charlier Type A series is generalized to the multidimensional case.     

高速高精度A/D转换器

本文介绍了用于观测太阳磁场的天文望远镜系统的高速高精度局部级联式多阈值A/D转换器。文章着重讨论了,为实现高速、高精度所采用的技术要点,并提出了研制高速高精度A/D转换器所必须考虑的有关问题。 我们所研制的A/D转换器,分辨率为1mV,相对误差0.025％,字长12位,前面接采样保持电路后,速度为10万次/秒。     

A stereo audio sigma-delta A/D-converter

A stereo sigma delta A/D-converter for audio applications is presented. In this converter, two identical cascaded fourth-order sigma-delta modulators and a sophisticated multistage linear-phase FIR decimation filter with oversampling ratio of 64 are implemented on the same die. The analog part is designed to operate at a low voltage with a low power consumption. Techniques to achieve simultaneously a high performance and a low power consumption are discussed in details. The minimum stopband attenuation of the decimator is more than 120 dB and the passband ripple of the overall converter is less than 0.0003 dB. The first decimation stage is a special tapped comb filter, whereas the remaining stages are realized without general multipliers by simultaneously implementing all the filter coefficients by using special bit-serial networks. For the integrated overall stereo converter, the power consumption and the signal-to-noise ratio are 180 mW and 97 dB (85 mW and 95 dB) for a 5 V (3 V) power supply. The circuit die area is only 4.7 mm×5.5 mm using a 1.2 μm double-poly BiCMOS process     

A superconducting tracking A/D converter

The design and fabrication of a superconducting A/D converter using Josephson technology are described. The 4-b A/D converter circuit was fabricated using a ten-level all-Nb technology. It uses a self-aligned lift-off process to define the Nb-Al₂O₃ -Nb Josephson junctions. Results from experiments performed on the prototype system at a few kilohertz sampling rate are presented