华硕P4T-E

华硕此款采用Intel 850芯片组的P4T-E主板,可支持Socket 478规格的Pentium 4系列处理器,且配合的内存为Rambus结构的RDRAM.除了具有高内存带宽的优势外,其余对于外围设备的支持都还算不错.     

AMD推出最新笔记本专用Athlon XP处理器

AMD发布了最新版笔记本电脑专用的Athlon XP处理器,它采用130纳米制造工艺,以Thoroughbred为处理器核心。同时,该公司调整了台式电脑与服务器版处理器的售价,最高降幅达28％。 AMD选择将Thoroughbred率先用在笔记本电脑,是因为该芯片的低耗电量特性。该芯片的系统总线速度也比以前的Athlon 4处理器为高,因此芯片与内存之间的数据传输速度更快。新芯片总线速度增加至266MHz,另外也可选择200MHz版本。     

网络处理器芯片的国产化之路

网络处理器芯片是构建网络通信设备的核心器件,设计复杂,研发投入巨大,国产化难度较高。本文试图在充分分析网络处理器设计挑战及技术发展趋势的基础上,提出一条切实可行的网络处理器芯片国产化之路。     

IBM正在研制每秒运算1．6亿万亿次的超级计算机

据报道．IBM公司正在努力研制其Power7处理器．并宣布其最新的超级计算机的核心将采用32个内核的Power7处理器芯片。这种芯片将配置大量的嵌入式DRAM内存。     

基于8086的SRAM读写控制仿真实现

设计了基于INTEL微处理器8086的SRAM读写控制系统,采用74LS373芯片构建地址锁存器,以静态随机访问存储器62256为内存芯片,并通过8255A驱动共阳极8位数码管实时显示内存值。在PROTEUS环境下进行了仿真,实现了内存读写访问控制,并验证了8086下特有的奇偶存储体读写访问模式。     

基于945G平台的工业级ATX母板 具有丰富的扩展接口，双千光位以太网口提供了冗余功能

基于Intel 945G平台的工业级ATX母板AIMB-762支持LGA775的Pentium D双核处理器、Pentium 4处理器和Celeron处理器，内建Intel 9450芯片组，支持3．8GHz的处理器，系统总线支持到533／800MHz，最高支持10．70B／s的带宽和4GB内存，双通道DDRII533／677内存增强了处理能力和提升了内存效能，并支持64位系统。内建的GMA950集成显卡支持224MB的共享内存，提供双头显示。     

掌上办公室4款轻巧UMPC

三星Q1-F000处理器Intel Pentium M(Dothan)723(1.0GHz)内存1GB硬盘60GB屏幕7英寸显示芯片集成Intel GMA900重量约0.777Kg索尼VGN-UX17C处理器Intel Celeron M423(1.06GHz)内存512MB硬盘30GB屏幕4.5英寸显示芯片集成Intel GMA950重量约0.517Kg华硕R2H处理器Intel Celeron M353(     

可伸缩系统趋向无缝连接

随着网络处理器成为互联网应用的主要构建模块,在将多个网络处理器进行无缝连接的技术方面竞争非常激烈。无缝连接意味着不需要依赖昂贵的ASIC集成方案即可建造可伸缩的系统。 Vitesse Semiconductor公司推出了一款称为FOCUS Connect的自路由(Self-routing)交换芯片,网络OEM制造商利用这一芯片即可拥有伸缩系统容量的能力,同时可降低总成本,并且不需要用ASIC或FPGA充当集成的连接逻辑。VSC2708 FOCUS Connect芯片将是无缝连接网络处理器/结构解决方案的先驱。VSC2708 FOCUS Connect交换芯片和IQ2000网络处理器系列的…     

网络处理器Intel IXP1200应用

网络处理器是近年来新出现的一类专用于网络通信设备中的微处理器芯片,它综合了RISC芯片和ASIC的优点。本文介绍了网络处理器技术和lntel公司IXP1200芯片的结构及应用特点,同时分析了提高处理性能的关键。     

64位UltraSPARC TM IIe处理器与用户见面

Ｓｕｎ公司于近日推出ＵｌｔｒａＳＰＡＲＣ处理器中的新品－ＵｌｔｒａＳＰＡＲＣ ＴＭ ＩＩｅ处理器。 该处理器是首个服务嵌入应用系统的高度集成的６４位产品,适用于遇信、网络某础设施和ＩＳＰ市场。该处理器具备高集成度,可减少功耗和芯片数、降低系统整体成本等性能。Ｓｕｎ对中芯片结构做了和精心设计,内部集成了２５６ＫＢ二级高速缓存、３２位标准 ６６ＭＨｚ ＰＣＩ总线、高性能 ＳＤＲＡＭ控制器和内存接口。该处理器的功耗性能是专为嵌入应用而优化的,对１．５优的４００ＭＨｚ处理器来说,其功耗估计最多为８瓦,而１．７…     

Efficient Multimatch Packet Classification for Network Security Applications

New network applications like intrusion detection systems and packet-level accounting require multimatch packet classification, where all matching filters need to be reported. Ternary content addressable memories (TCAMs) have been adopted to solve the multimatch classification problem due to their ability to perform fast parallel matching. However, TCAMs are expensive and consume large amounts of power. None of the previously published multimatch classification schemes are both memory and power efficient. In this paper, we develop a novel scheme that meets both requirements by using a new set splitting algorithm (SSA). The main idea behind SSA is that it splits filters into multiple groups and performs separate TCAM lookups into these groups. It guarantees the removal of at least 1/2 the intersections when a filter set is split into two sets, thus resulting in low TCAM memory usage. SSA also accesses filters in the TCAM only once per packet, leading to low-power consumption. We compare SSA with two best known schemes: multimatch using discriminators (MUD) (Lakshminarayanan and Rangarajan, 2005) and geometric intersection-based solutions (Yu and Katz, 2004). Simulation results based on the SNORT filter sets show that SSA uses approximately the same amount of TCAM memory as MUD, but yields a 75%–95% reduction in power consumption. Compared with geometric intersection-based solutions, SSA uses 90% less TCAM memory and power at the cost of one additional TCAM lookup per packet. We also show that SSA can be combined with SRAM/TCAM hybrid approaches to further reduce energy consumption.     

TCAM/CAM-QCA: (Ternary) Content Addressable Memory using Quantum-dot Cellular Automata

This paper describes a Content Addressable Memory (CAM) architecture and its ternary variant called Ternary Content Addressable Memory (TCAM) using the Quantum-dot Cellular Automata (QCA). QCA is an alternative to the current integrated circuit (CMOS) paradigm based on the characteristics of confinement and mutual repulsion between electrons. It is expected to run with clocks in high frequency (in THz order), in nanometers scale and with very low energy consumption. First, this work presents the basic building blocks (1-bit memory cell, array of memory cells, ternary memory line and encoder). Then, we describe the complete TCAM and CAM architectures. Finally, the proposed architectures are tested and validated using QCADesigner simulator, attesting their functionalities. If QCA consolidates as a possible CMOS substitute, this study can impact the design of future components that uses TCAM and CAM such as routers and switches respectively.     

一种基于Bloom-filter表项压缩的TCAM业务识别算法

在三态内容寻址存储器(Ternary Content Addressable Memory, TCAM)表项宽度和存储容量约束下,该文提出一种基于匹配表项压缩的BF-TCAM算法,采用Bloom-Filter(BF)对匹配关键字进行单字节编码压缩关键字长度,解决了匹配吞吐率低和存储空间不足问题。针对BF在表项压缩过程带来的冲突率上升问题,引入向量存储空间策略,利用向量存储空间实现多个哈希函数映射,相对于比特向量策略,有利于降低匹配冲突率。测试实验表明,相对于传统的TCAM匹配算法,BF-TCAM算法不但提高了匹配吞吐率和存储空间利用率,同时可有效降低BF压缩产生的冲突率。     

Efficient location of free spaces in TCAM to improve router performance

A ternary content‐addressable memory (TCAM) is a popular hardware device for performing fast IP‐address lookup. Because keeping all entries sorted in TCAM, we need move the entries for inserting a new entry. In this paper, we have presented a scheme for minimizing route update overheads in TCAM‐based forwarding engines. Our optimizations are based on the hierarchy of prefixes in the routing table. The number of memory movement per update depends on the sequence of the new‐inserted prefixes, instead of the initial prefixes in routing table. For the real route update traces, the average number of movements is less than 0.01. Further, when compared to an existing optimization algorithm, in the average case, our algorithm shows a 90% reduction in movement overheads. Copyright © 2005 John Wiley & Sons, Ltd.     

A TCAM-based distributed parallel IP lookup scheme and performance analysis

Using ternary content addressable memory (TCAM) for high-speed IP address lookup has been gaining popularity due to its deterministic high performance. However, restricted by the slow improvement of memory accessing speed, the route lookup engines for next-generation terabit routers demand exploiting parallelism among multiple TCAM chips. Traditional parallel methods always incur excessive redundancy and high power consumption. We propose in this paper an original TCAM-based IP lookup scheme that achieves both ultra-high lookup throughput and optimal utilization of the memory while being power-efficient. In our multi-chip scheme, we devise a load-balanced TCAM table construction algorithm together with an adaptive load balancing mechanism. The power efficiency is well controlled by decreasing the number of TCAM entries triggered in each lookup operation. Using four 133 MHz TCAM chips and given 25% more TCAM entries than the original route table, the proposed scheme achieves a lookup throughput of up to 533 MPPS while remains simple for ASIC implementation.     

一种实现TCAM快速增量更新的算法

三重内容可寻址存储器TCAM（ternary content-addressable memory）是执行快速路由查找的常用硬件设备。在TCAM中进行最长前缀匹配操作最糟糕情况可能需要次存储操作，这里提出了一种算法来处理TCAM，结果使增量更新时间在最糟糕情况保持较小。通过对该算法与其他算法的性能分析，证明该算法在前缀长度排序限制条件下较常用算法更优。     

一种嵌入铁电晶体管内容寻址存储器的高能效浮点运算结构

随着数据密集型应用的日益增多,内存墙问题已成为制约计算效率的瓶颈。该文提出一种新型的浮点数(FP)运算结构,该结构嵌入了基于铁电场效应晶体管(FeFET)的三元内容寻址存储器(TCAM)以实现高效的计算。通过特定规则设计的超高密度TCAM结构,可以用能效更高的TCAM搜索操作代替部分传统浮点运算,从而节约整体能耗。仿真实验证明,该文所提结构和运算执行流程,与常规浮点运算单元(FPU)相比,可以降低多达33%的能耗。     

90 nm TCAM cell design with leakage suppression technique

A leakage suppressed ternary content-addressable memory (TCAM) cell design is introduced, in which `don?t care? information is used to minimise the leakage power dissipated in the prefix CAM. The measurements based on 90 nm process technology show that without any performance penalty the design can deliver a leakage power reduction of 18%.     

Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed

With a great scalability potential, nonvolatile magnetoresistive memory with spin-torque transfer (STT) programming has become a topic of great current interest. This paper addresses cell structure design for STT magnetoresistive RAM, content addressable memory (CAM) and ternary CAM (TCAM). We propose a new RAM cell structure design that can realize high speed and reliable sensing operations in the presence of relatively poor magnetoresistive ratio, while maintaining low sensing current through magnetic tunneling junctions (MTJs). We further apply the same basic design principle to develop new cell structures for nonvolatile CAM, and TCAM. The effectiveness of the proposed RAM, CAM and TCAM cell structures has been demonstrated by circuit simulation at 0.18 $ mu$m CMOS technology.      

A priority TCAM IP-routing lookup scheme

A priority TCAM IP-routing lookup scheme, which combines a priority ternary content addressable memory (TCAM) technique with a compact IP-routing lookup scheme, is proposed in this paper. It not only completes an IP-routing lookup with two memory accesses but also achieves small lookup table size and fast table reconstruction time.