具有SiO2/SiNX/SiO2 复合绝缘层的有机薄膜晶体管

We have investigated a SiO_2/SiN_x/SiO_2 composite insulation layer structured gate dielectric for an organic thin film transistor(OTFT) with the purpose of improving the performance of the SiO_2 gate insulator. The SiO_2/SiN_x/SiO_2 composite insulation layer was prepared by magnetron sputtering.Compared with the same thickness of a SiO_2 insulation layer device,the SiO_2/SiN_x/SiO_2 composite insulation layer is an effective method of fabricating OTFT with improved electric characteristics and decrease...     

Organic thin film transistors with PMMA modified insulator

A double insulation layer structure organic thin films transistor (OTFT) was investigated for improving the performance of the SiO2 gate insulator. A 50 nm PMMA layer was coated on top of the SiO2 gate insulator as the organic insulator layer. The results demonstrated that using inorganic/organic compound insulator as the gate dielectric layer is an effective method to fabricate OTFTs with improved electric characteristics and decreased leakage current. Electrical parameters of carrier mobility and on/off ratio were calculated. OTFT based on Si substrate with a field-effect mobility of 4.0 × 10-3cm2/Vs and on/off ratio of 104 was obtained.     

在SiO2中掺Al对Au/纳米(SiO2/Si/SiO2)/p-Si 结构电致发光的影响

利用射频磁控溅射方法,制成纳米SiO2层厚度一定而纳米Si层厚度不同的纳米(SiO2/Si/SiO2)/p-Si结构和纳米(SiO2∶Al/Si/SiO2∶Al)/p-Si结构,用磁控溅射制备纳米SiO2∶Al时所用的SiO2/Al复合靶中的Al的面积百分比为1%．上述两种结构中Si层厚度均为1—3nm,间隔为0.2nm．为了对比研究,还制备了Si层厚度为零的样品．这两种结构在900℃氮气下退火30min,正面蒸半透明Au膜,背面蒸Al作欧姆接触后,都在正向偏置下观察到电致发光（EL）．在一定的正向偏置下,EL强度和峰位以及电流都随Si层厚度的增加而同步振荡,位相相同．但掺Al结构的发光强度普遍比不掺Al结构强．另外,这两种结构的EL具体振荡特性有明显不同．对这两种结构的电致发光的物理机制和SiO2中掺Al的作用进行了分析和讨论．     

磁控溅射法制备复合绝缘层的薄膜晶体管

研究了磁控溅射法制备的复合绝缘层结构的有机薄膜晶体管.该器件是以酞菁铜(CuPc)作为有源层,SiO2/Si3N4/SiO2复合绝缘层和单层SiO2为绝缘层来进行对比研究的.结果显示与单层SiO2绝缘层的器件相比,具有复合绝缘层的器件结构能有效改进有机薄膜晶体管的性能.同时发现,不同厚度的SiO2/Si3N4/SiO2复合绝缘层对晶体管的性能也有影响,绝缘层太厚,感应电流小;绝缘层太薄,器件容易被击穿.     

具有双绝缘层和修饰电极的薄膜场效应晶体管

研究了具有OTS/SiO2双绝缘层结构及MoO3/Al电极结构的有机薄膜晶体管.器件是以热生长的Si02作为有机薄膜晶体管的栅绝缘层,酞菁铜作为有源层的.OTS/SiO2双绝缘层的结构提高了器件的场效应迁移率和开关电流比,降低了阈值电压.实验表明在同样的栅极电压下,具有MoO3/Al电极的器件和金电极的器件有着相似的源漏输出电流.结果显示具有OTS/SiO2双绝缘层及MoO3/Al电极结构的器件能有效改进有机薄膜晶体管的性能.     

具有双绝缘层和修饰电极的薄膜场效应晶体管

研究了具有OTS/SiO2双绝缘层结构及MoO3/Al电极结构的有机薄膜晶体管.器件是以热生长的Si02作为有机薄膜晶体管的栅绝缘层,酞菁铜作为有源层的.OTS/SiO2双绝缘层的结构提高了器件的场效应迁移率和开关电流比,降低了阈值电压.实验表明在同样的栅极电压下,具有MoO3/Al电极的器件和金电极的器件有着相似的源漏输出电流.结果显示具有OTS/SiO2双绝缘层及MoO3/Al电极结构的器件能有效改进有机薄膜晶体管的性能.     

SiO2/4H-SiC界面氮化退火

通过1 300℃高温干氧热氧化法在n型4H-SiC外延片上生长了厚度为60 nm的SiO2栅氧化层.为了开发适合于生长低界面态密度和高沟道载流子迁移率的SiC MOSFET器件产品的栅极氧化层退火条件,研究了不同退火条件下的SiO2/SiC界面电学特性参数.制作了MOS电容和横向MOSFET器件,通过表征SiO2栅氧化层C-V特性和MOSFET器件I-V特性,提取平带电压、C-V磁滞电压、SiO2/SiC界面态密度和载流子沟道迁移率等电学参数.实验结果表明,干氧氧化形成SiO2栅氧化层后,在1 300℃通入N2退火30 min,随后在相同温度下进行NO退火120 min,为最佳栅极氧化层退火条件,此时,SiO2/SiC界面态密度能够降低至2.07×1012 cm-2·eV-1@0.2 eV,SiC MOSFET沟道载流子迁移率达到17 cm2·V-1·s-1.     

表面修饰的ZnPc薄膜晶体管性能研究

以热生长的SiO2作为栅绝缘层,酞菁锌(ZnPc)作为有源层,研究了具有十八烷基三氯硅烷(OTS,C18H37SiCl3)/SiO2双绝缘层结构的有机薄膜晶体管(OTFT)。实验表明,采用OTS可以有效地降低SiO2栅绝缘层的表面能并改善表面的平整度,器件的场效应迁移率提高了3.5倍,漏电流从10-9A降到10-10A,阈值电压降低了5 V,开关电流比从103增加到104。结果显示,具有OTS/SiO2双绝缘层的器件结构能有效改进OTFT的性能。     

Low-frequency noise behavior of SiO/sub 2/--HfO/sub 2/ dual-layer gate dielectric nMOSFETs with different interfacial oxide thickness

The low-frequency noise has been studied in nMOSFETs with an HfO/sub 2/--SiO/sub 2/ gate stack, for different thickness of the SiO/sub 2/ interfacial layer (IL). It is observed that the 1/f-like noise in linear operation, is about 50 times higher in the HfO/sub 2/ devices with a 0.8-nm chemical oxide IL, compared with the 4.5-nm thermal oxide reference n-channel transistors. This is shown to relate to the correspondingly higher trap density in the dielectric material. In addition, it is demonstrated that the noise rapidly reduces with increasing thickness of the IL. From the results for a 2.1-nm SiO/sub 2/ IL, it is derived that at a certain gate voltage range, electron tunneling to a defect band in the HfO/sub 2/ layer may contribute to a pronounced increase in the flicker noise.     

Determination of tunnel mass and physical thickness of gate oxide including poly-Si/SiO/sub 2/ and Si/SiO/sub 2/ interfacial transition Layers

By including poly-Si/SiO/sub 2/ and Si/SiO/sub 2/ interfacial transition (IFT) layers, an excellent agreement in terms of both C-V and J-V characteristics is obtained between the experiment and theory for both polarities of gate voltage (V/sub G/) for the first time. The highly precise physical models for gate depletion and gate accumulation bring an oxide thickness extracted from the C-V fitting in a negative V/sub G/ close to that extracted in a positive V/sub G/. It is shown that the physical oxide thickness should be regarded as a distance between the middle points inside the IFT layers in both sides of the gate oxide. In addition, it is found that the tunnel mass is independent of the gate-oxide thickness from 14 to 28 /spl Aring/. It is also shown that the oxide-thickness dependence of the tunnel mass , is ascribable to the C-V-J-V fitting only in the case of a negative polarity of V/sub G/ while neglecting the poly-Si/SiO/sub 2/ IFT layer.     

具有无机有机双绝缘层和修饰电极的薄膜晶体管

研究了有机薄膜晶体管器件.器件是以热生长的SiO2作为有机薄膜晶体管的栅绝缘层,酞菁铜作为有源层的.实验表明采用一种硅烷耦合剂-十八烷基三氯硅烷(OTS)修饰SiO2可以有效地降低栅绝缘层的表面能从而明显提高了器件的性能.器件的场效应迁移率提高了2.5倍、阈值电压降低了3 V、开关电流比从103增加到104.同时我们采用MoO3修饰铝作为器件的源漏电极,形成MoO3/Al双层电极结构.实验表明在同样的栅极电压下,具有MoO3/Al 电极的器件和金电极的器件有着相似的源漏输出电流Ids.结果显示具有OTS/SiO2双绝缘层的及MoO3/Al 电极结构的器件能有效改进有机薄膜晶体管的性能.     

Thermal Nitridation of Si and SiO/sub 2/ for VLSI

This paper presents an extensive review of our work on thermal nitridation of Si and SiO/sub 2/. High-quality ultrathin films of silicon nitride and nitrided-oxide (nitroxide) have been thermally grown in ammonia atmosphere in a cold-wall RF-heated reactor and in a lamp-heated system. The growth kinetics and their dependence on processing time and temperature have been studied from very short to long nitridation times. The kinetics of thermal nitridation of SiO/sub 2/ in ammonia ambient have also been studied. In nitroxide, nitrogen-rich layers are formed at the surface and interface at a very early stage of the nitridation. Then the nitridation reaction mainly goes on in the bulk region with the surface and near interface nitrogen content remaining fairly constant. Our results also indicate the formation of an oxygen-rich layer at the interface underneath the nitrogen-rich layer whose thickness increases slowly with nitridation time. The nitride and nitroxide films were analyzed using Auger electron spectroscopy, grazing angle Rutherford backscattering, and etch rate measurements. MIS devices were fabricated using these films as gate insulators and were electrically characterized using I-V, C-V, time-dependent breakdown, trapping, and dielectric breakdown techniques. Breakdown, conduction, and C -V measurements on metal-insulator semiconductor (MIS) structures fabricated with these films show that very thin thermal silicon nitride and nitroxide films can be used as gate dielectrics for future highly scaled-dowm VLSI devices. The electrical characterization results also indicate extremely low trapping in the nitride films. The reliability of ultrathin nitride was observed to be far superior to SiO/sub 2/ and nitroxide due to its much less trapping. Studies show that the interface transition from nitride to silicon is almost abrupt and the morphology and roughness of the interface are comparable to the SiO/sub 2/-Si interfaces.     

具有双绝缘层的有机薄膜晶体管

为了提高SiO2单绝缘层器件的性能,在SiO2绝缘层的表面用旋涂的方法制备一层大约50 nm厚度的PMMA.实验结果表明用无机/有机双绝缘层可以有效的提高器件的性能同时降低器件的漏电流.计算出了载流子迁移率和开关电流比,基于PMMA/SiO2双绝缘层器件的载流子迁移率和开关电流比分别是4.0×10-3cm2/Vs和104.     

Charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes

A detailed study on charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes has been carried out. Due to the inherent asymmetry of the dual layer stack all electrical properties studied were found to be strongly polarity dependent. The gate current is strongly reduced for injection from the TiN (gate) electrode compared to injection from the n-type Si substrate. For substrate injection, electron trapping occurs in the bulk of the Al/sub 2/O/sub 3/ film, whereas for gate injection mainly hole trapping near the Si substrate is observed. Furthermore, no significant interface state generation is evident for substrate injection. In case of gate injection a rapid build up of interface states occurs already at small charge fluence (q/sub inj/ /spl sim/ 1 mC/cm/sup 2/). Dielectric reliability is consistent with polarity-dependent defect generation. For gate injection the interfacial layer limits the dielectric reliability and results in low Weibull slopes independent of the Al/sub 2/O/sub 3/ thickness. In the case of substrate injection, reliability is limited by the bulk of the Al/sub 2/O/sub 3/ layer leading to a strong thickness dependence of the Weibull slope as expected by the percolation model.     

新型SiO2栅介质非晶硅薄膜晶体管室温红外探测器

对用作室温红外探测敏感单元的非晶硅薄膜晶体管进行了研究，提出了一种新型SiO2栅介质非晶硅薄膜晶体管室温红外探测器。该探测器的基本工作机理与传统的SiN2栅介质薄膜晶体管相类似，但在器件性能方面不仅具有较高的响应度，而且具有更好的温度稳定性；在制作工艺方面具有更高的工艺重复性和栅介质淀积的均匀性。     

Organic thin-film field-effect transistors with MoO3/Al electrode and OTS/SiO2 bilayer gate insulator

An organic thin-film transistor (OTFTs) having OTS/SiO₂ bilayer gate insulator and MoO₃/Al electrode configuration between gate insulator and source–drain (S–D) electrodes has been investigated. Thermally grown SiO₂ layer is used as the OTFT gate dielectric and copper phthalocyanine (CuPc) for an active layer. We have found that using silane coupling agents, octadecyltrichlorosilane (OTS) on SiO₂, surface energy of SiO₂ gate dielectric is reduced; consequently, the device performance has been improved significantly. This OTS/SiO₂ bilayer gate insulator configuration increases the field-effect mobility, reduces the threshold voltage and improves the on/off ratios simultaneously. The device with MoO₃/Al electrode has similar source–drain current (I_DS) compared to the device with Au electrode at same gate voltage. Our results indicate that using double-layer of insulator and modified electrode is an effective way to improve OTFT performance.     

SiO/sub 2//AlGaN/InGaN/GaN MOSDHFETs

The characteristics of a novel nitride based field-effect transistor combining SiO/sub 2/ gate isolation and an AlGaN/InGaN/GaN double heterostructure design (MOSDHFET) are reported. The double heterostructure design with InGaN channel layer significantly improves confinement of the two-dimensional (2-D) electron gas and compensates strain modulation in AlGaN barrier resulting from the gate voltage modulations. These decrease the total trapped charge and hence the current collapse. The combination of the SiO/sub 2/ gate isolation and improved carrier confinement/strain management results in current collapse free MOSDHFET devices with gate leakage currents about four orders of magnitude lower than those of conventional Schottky gate HFETs.     

Carrier mobility in p-MOSFET with atomic-layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics

P/sup +/-poly-Si gate MOS transistors with atomic-layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics (EOT=2.50 nm) have been fabricated. Similar to the reference samples with SiO/sub 2/ gate dielectrics (T/sub ox/=2.45 nm), clear saturation characteristics of drain current are obtained for the samples with stack gate dielectrics. Identical hole-effective mobility is obtained for the samples with the SiO/sub 2/ and the stack gate dielectrics. The maximum value of hole-effective mobility is the same (54 cm/sup 2//Vs) both for the stack and the SiO/sub 2/ samples. Hot carrier-induced mobility degradation in transistors with the stack gate dielectrics was found to be identical to that in transistors with the SiO/sub 2/ gate dielectrics. In addition to the suppression of boron penetration, better TDDB characteristics, and soft breakdown free phenomena for the stack dielectrics (reported previously), the almost equal effective mobility (with respect to that of SiO/sub 2/ dielectrics) has ensured the proposed stack gate dielectrics to be very promising for sub-100-nm technology generations.     

Characteristics and mechanism of tunable work function gate electrodes using a bilayer metal structure on SiO/sub 2/ and HfO/sub 2/

In this letter, we investigate a method to adjust the gate work function of an MOS structure by stacking two metals with different work functions. This method can provide work function tunability of approximately 1 eV as the bottom metal layer thickness is increased from 0 to about 10 nm. This behavior is demonstrated with different metal combinations on both SiO/sub 2/ and HfO/sub 2/ gate dielectrics. We use capacitance-voltage (C-V) characteristics to investigate the effect of different annealing conditions and different metal/metal bilayer couples on the work function. By comparing the as-deposited and annealed films, and by comparing with metals that are relatively inert with each other, we deduce that the work function tuning behavior likely involves metal/metal interdiffusion.     

Flexible AM OLED panel driven by bottom-contact OTFTs

Active matrix organic-light-emitting-diode (AM OLED) panels, driven by organic thin-film transistors (OTFT), have been successfully fabricated on a flexible plastic substrate. The pixel circuit consists of two bottom-contact pentacene OTFTs working as switching and driving transistors. The panel has 16 /spl times/ 16 pixels, each of which have an OLED using a phosphorescent material with an emission efficiency of 30 cd/A. A tantalum oxide (Ta/sub 2/O/sub 5/) film with a dielectric constant of 24, prepared by the anodization of Tantalum (Ta), was used as the gate insulator of the OTFTs. The passivation layer on the OTFTs was formed by a layer of silicon dioxide (SiO/sub 2/) and two layers of polyvinyl alcohol. Using OTFTs with a Ta/sub 2/O/sub 5/ gate insulator, the authors have realized a flexible active matrix OLED panel driven with a low voltage of -12 V.