Simulating and modeling the breakdown voltage in a semi-insulating GaAs P+N junction diode

This work aims to determine the characteristic PN junction diode, subject to a reverse polarization, while I （breakdown voltage） of the inverse current in a GaAs specifying the parameters that influence the breakdown voltage of the diode. In this work, we simulated the behavior of the ionization phenomenon by impact breakdown by avalanche of the PN junctions, subject to an inverse polarization. We will take into account both the trapping model in a stationary regime in the P＋N structure using like material of basis the Ⅲ-Ⅴ compounds and mainly the GaAs semi-insulating in which the deep centers have in important densities. We are talking about the model of trapping in the space charge region （SCR） and that is the trap density donor and acceptor states. The carrier crossing the space charge region （SCR） of W thickness creates N electron-hole pairs： for every created pair, the electron and the hole are swept quickly by the electric field, each in an opposite direction, which comes back, according to an already accepted reasoning, to the crossing of the space charge region （SCR） by an electron or a hole. So the even N pair created by the initial particle provoke N2 ionizations and so forth. The study of the physical and electrical behaviour of semiconductors is based on the influence of the presence of deep centers on the characteristic I（V） current-tension, which requires the calculation of the electrostatic potential, the electric field, the integral of ionization, the density of the states traps, the diffusion current of minority in the regions （1） and （3）, the current thermal generation in the region （2）, the leakage current in the surface, and the breakdown voltage.     

电力静电感应晶体管大电压特性的改善

A novel structure for designing and fabricating a power static induction transistor（SIT）with excellent high breakdown voltage performance is presented.The active region of the device is designed to be surrounded by a deep trench to cut off the various probable parasitical effects that may degrade the device performance,and to avoid the parallel-current effect in particular.Three ring-shape junctions（RSJ）are arranged around the gate junction to reduce the electric field intensity.It is important to achieve maximum gate–source breakdown voltage BVGS, gate–drain breakdown voltage BVGD and blocking voltage for high power application.A number of technological methods to increase BVGD and BVGS are presented.The BVGS of the power SIT has been increased to 110 V from a previous value of 50–60 V,and the performance of the power SIT has been greatly improved.The optimal distance between two adjacent ring-shape junctions and the trench depth for the maximum BVGS of the structure are also presented.     

基于一种可靠非均匀场限环终端结构的1.4kV 4H型碳化硅PiN二极管

This paper presents the design and fabrication of an effective, robust and process-tolerant floating guard ring termination on high voltage 4H-SiC PiN diodes. Different design factors were studied by numerical simulations and evaluated by device fabrication and measurement. The device fabrication was based on a 12 μm thick drift layer with an N-type doping concentration of 8 × 10^15 cm^-3. P^＋ regions in the termination structure and anode layer were formed by multiple aluminum implantations. The fabricated devices present a highest breakdown voltage of 1.4 kV, which is higher than the simulated value. For the fabricated 15 diodes in one chip, all of them exceeded the breakdown voltage of 1 kV and six of them reached the desired breakdown value of 1.2 kV.     

Conductivity modulation enhanced lateral IGBT with SiO2 shielded layer anode by SIMOX technology on SOI substrate

New Lateral IGBT with SiO2 shielded layer anode on SOI substrate is proposed and discussed. Compared to the conventional LIGBT, the proposed device offers a conductivity modulation enhanced effect due to the SiO2 shielded layer anode structure which can be formed by SIMOX technology. Simulation results show that, for the proposed LIGBT, during conducting state, the electron-hole plasma concentrations in n-drift region are several times larger than that of conventional LIGBT; the conducting current is up to 37% larger than that of conventional one. The SiO2 shielded layer anode conductivity modulation enhanced effect do not sacrifice other characteristics of device, such as breakdown and switching, but is compatible to other optimized technologies.     

非穿通型与穿通型平行平面结基于Chynoweth方法的新的设计表达式

The relations among the breakdown voltage,the width and the concentration of the voltage-sustaining layer for the non-punch-through(NPT) and punch-through(PT) abrupt parallel-plane junctions have been reestablished based on the ionization integral by the Chynoweth model,distinguished from the conventional results obtained by the Fulop model.The numerical calculation results indicate that the new expressions are more accurate than those in previous literature.While the breakdown voltage of the NPT case varied from 400 to 1600 V using the Chynoweth model,the value using the Fulop model is overestimated by 12%(478 V) to 18%(1895 V).For the PT case with optimum design of the specific on-resistance,when the breakdown voltage is varied from 400 to 1600 V,the width and concentration are from 81.0168%to 80.2416%and from 91.4341%to 91.6941%of those of the NPT cases,respectively.The relations between the specific on-resistance and the breakdown voltage for both the NPT and PT structures are also established.Simulation results by MEDICI show good agreement with the proposed expressions.     

A NEW STRUCTURE AND ITS ANALYTICAL BREAKDOWN MODEL OF HIGH VOLTAGE SOI DEVICE WITH STEP UNMOVABLE SURFACE CHARGES OF BURIED OXIDE LAYER

A new SOI （Silicon On Insulator） high voltage device with Step Unmovable Surface Charges （SUSC） of buried oxide layer and its analytical breakdown model are proposed in the paper. The unmovable charges are implemented into the upper surface of buried oxide layer to increase the vertical electric field and uniform the lateral one. The 2-D Poisson＇s equation is solved to demonstrate the modulation effect of the immobile interface charges and analyze the electric field and breakdown voltage with the various geometric parameters and step numbers. A new RESURF （REduce SURface Field） condition of the SOl device considering the interface charges and buried oxide is derived to maximize breakdown voltage. The analytical results are in good agreement with the numerical analysis obtained by the 2-D semiconductor devices simulator MEDICI. As a result, an 1200V breakdown voltage is firstly obtained in 3pro-thick top Si layer, 2pro-thick buried oxide layer and 70pro-length drift region using a linear doping profile of unmovable buried oxide charges.     

INCREASING BREAKDOWN VOLTAGE OF LDMOST USING BURIED LAYER

A new LDMOST structure,named B-LDMOST that has a buried layer under the drain is proposed.The buried layer is not connected to the drift region,so it can optimize the vertical field distribution and increase breakdown voltage.The analysis and the simulated results show that B-LDMOST can increase breakdown voltage,with almost negligible influence on the other parameters such as on-resistance,switching time,and so om.     

漂移区阶梯掺杂的双栅SOI LDMOS研究

A new double gate SOI LDMOS with a step doping profile in the drift region is proposed. The structure is characterized by one surface gate and another embedded gate under the P-body region. The broadened current flow path and the majority carrier accumulation layer on the side wall of the embedded gate reduce the specific on-resistance （Ron, sp）. The electric field distribution is improved due to the embedded gate and step doping profile, resulting in a high breakdown voltage （BV） and low Ron, sp. The influences of device parameters on BV and Ron, sp are investigated by simulation. The results indicate that BV is increased by 35.2% and Ron, sp is decreased by 35.1% compared to a conventional SOI LDMOS.     

700V折叠漂移区高压器件新结构

A new high-voltage LDMOS with folded drift region(FDR LDMOS) is proposed. The drift region is folded by introducing the interdigital oxide layer in the Si active layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance.     

一种高速雪崩光电探测器

High-speed avalanche photodiodes are widely used in optical communication systems. Nowadays, separate absorption charge and multiplication structure is widely adopted. In this article, a structure with higher speed than separate absorption charge and multiplication structure is reported. Besides the traditional absorption layer, charge layer and multiplication layer, this structure introduces an additional charge layer and transit layer and thus can be referred to as separate absorption, charge, multiplication, charge and transit structure. The introduction of the new charge layer and transit layer brings additional freedom in device structure design. The benefit of this structure is that the carrier transit time and device capacitance can be reduced independently, thus the 3 dB bandwidth could be improved by more than 50% in contrast to the separate absorption charge and multiplication structure with the same size.     

4500V SPT IGBT 动静态损耗优化

本文关注高压IGBT动静态性能的优化。对4500V增强型平面IGBT进行研究,该结构在阴极一侧具有载流子存储层。其中垂直结构采用软穿通(SPT)结构,顶部结构采用增强型平面结构,该结构被称为SPT IGBT,仿真结果显示4500V SPT 具有软关断波形,与SPT结构相比提升了导通压降和关断损耗之间的折衷关系。同时,对不同载流子存储层掺杂浓度对动静态性能的影响也进行了研究,以此来优化SPT IGBT的动静态损耗。     

一种低功耗4H-SiC IGBT的仿真研究

针对传统沟槽栅4H-SiC IGBT关断时间长且关断能量损耗高的问题,文中利用Silvaco TCAD设计并仿真了一种新型沟槽栅4H-SiC IGBT结构。通过在传统沟槽栅4H-SiC IGBT结构基础上进行改进,在N ⁺缓冲层中引入两组高掺杂浓度P区和N区,提高了N ⁺缓冲层施主浓度,折中了器件正向压降与关断能量损耗。在器件关断过程中,N ⁺缓冲层中处于反向偏置状态的PN结对N ^-漂移区中电场分布起到优化作用,加速了N ^-漂移区中电子抽取,在缩短器件关断时间和降低关断能量损耗的同时提升了击穿电压。Silvaco TCAD仿真结果显示,新型沟槽栅4H-SiC IGBT击穿电压为16 kV,在15 kV的耐压设计指标下,关断能量损耗低至4.63 mJ,相比传统结构降低了40.41%。     

Reversible breakdown voltage collapse in silicon gate-controlled diodes

A reversible breakdown voltage collapse is recorded in the high voltage range of the junction breakdown voltage vs gate voltage characteristic of silicon gate-controlled diodes, which is explained in terms of a spatial switching of the avalanche breakdown within the device structure. The collapse gate voltage is oxide-thickness dependent and is accurately predictable as the avalanche breakdown voltage of the deeply depleted MOS capacitor within the gate-controlled diode structure.The minimum oxide thickness required for approaching the bulk-determined breakdown voltage in field-plated planar diodes and transistors is found to range from 0.01 to 5.00 μm for substrate impurity concentration from 10¹⁷ to 5 × 10¹⁴ cm^?3, according to a design plot provided in the paper.     

Impact ionization wave breakdown of drift step recovery diodes

High frequency IMPATT oscillations followed under certain conditions by reversible impact ionization wave breakdown of the p ⁺-n-n ⁺ diode structure have been experimentally observed for the first time in a drift step recovery diode operating in the avalanche breakdown mode after a fast voltage restoration of the p-n junction.     

MBE-grown HgCdTe multi-layer heterojunction structures for high speed low-noise 1.3–1.6 µm avalanche photodetectors

HgCdTe is an attractive material for room-temperature avalanche photodetectors (APDs) operated at 1.3–1.6 μm wavelengths for fiber optical communication applications because of its bandgap tunability and the resonant enhancement of hole impact ionization for CdTe fractions near 0.73. The HgCdTe based separate absorption and multiplication avalanche photodetector is designed and fabricated for backside illumination through a CdZnTe substrate. The multi-layer device structure is comprised of seven layers including 1). n ⁺ contact 2). n ⁻ diffusion buffer 3). n ⁻ absorber 4). n charge sheet 5). n ⁻ avalanche gain 6). p to form junction, and 7).p ⁺ contact. Several wafers were processed into 45 μm × 45 μm and 100 (μm × 100 μm devices. The mean value of avalanche voltage is 63.7 V measured at room temperature. At 1 GHz, the device shows a gain of about 7 for a gain-bandwidth product of 7 GHz. This first demonstration of an all molecular beam epitaxially grown HgCdTe multi-layer heterojunction structure on CdZnTe substrates represents a significant advance toward the goal of producing reliable room temperature HgCdTe high speed, low noise avalanche photodetectors.     

Novel buffer engineering: A concept for fast switching and low loss operation of planar IGBT

For the first time, an insulated gate bipolar transistor with a novel buffer is proposed and verified by two-dimensional (2D) mixed device-circuit simulations. The structure of the proposed device is almost identical with that of the conventional IGBT, except for the buffer layer which is formed by employing a three-step, gradually changing doping n⁺ structure. Compared with the conventional IGBT, the proposed device exhibits better trade-off relation between the conduction and switching losses. The turn-off time is halved from 9.4 μs of the conventional IGBT to 4.5 μs of the proposed device, so the operation speed of the proposed device is greatly improved. Further, the forward blocking voltage is enormously increased from 907 V of the proposed device to 1278 V of the proposed device, which is required for high power operation.     

A new technique in LDMOS transistors to improve the breakdown voltage and the lattice temperature

A new technique for high breakdown voltage of the LDMOS device is proposed in this paper. The main idea in the proposed technique is to insert the P⁺ silicon windows in the buried oxide at the interface of the n-drift to improve the breakdown voltage, electric field and maximum lattice temperature. The proposed structure is called as P⁺ window LDMOS (PW-LDMOS). It is shown by extending the depletion region between the P⁺ windows and the n-drift region, the breakdown voltage of PW-LDMOS increases to 405 V from 84 V of the conventional LDMOS on 1 µm silicon layer and 2 µm buried oxide layer. Also, effective values of doping, length, and depth of P⁺ window are investigated in the breakdown voltage. Moreover, a self-heating-effect is alleviated by the silicon windows in comparison with the conventional LDMOS. All the achieved results have been extracted by two-dimensional and two-carriers simulator ATLAS.     

The collector-base avalanche voltage of epitaxial transistors

The effect of a low resistivity substrate on the avalanche voltage characteristics of diffused epitaxial pnn⁺ junctions has been considered. Curves are given of the reduction in the “intrinsic” avalanche voltage and also of the movement of the depletion layer boundaries with junction voltage, thus aiding the process of optimizing the design of a transistor.     

SPT -IGBT的性能研究及优化

本文研究了一种改进型软穿通（SPT）IGBT结构,被称为SPT -IGBT,并给出了基于1200V器件结构的动静态特性以及所采用技术的仿真结果。在此基础上进一步对器件结构的优化进行了讨论。和传统结构相比,SPT -IGBT具有更低的饱和导通压降（VCE(sat)）和更优秀的开关特性,因此它非常适用于3000V以上的应用场合。同时,薄芯片厚度带来的高开关速度使得SPT -IGBT在1200V和1700V的应用领域也有着很强的竞争优势。     

Tunneling currents in In0.53Ga0.47As homojunction diodes and design of InGaAs/InP hetero-structure avalanche photodiodes

Tunneling currents in InGaAs homojunctions were studied from measurements of temperature dependence of breakdown voltage, current-voltage characteristics, tunneling effective mass, and noise spectrum. Zener emission dominates the reverse current prior to avalanche breakdown in the carrier concentration region of >10¹⁵ cm^?3 and restricts the avalanche gain in InGaAs homojunctions. An InGaAs/InP hetero-structure having a p-n junction in the InP layer was studied to reduce dark currents caused by Zener emission. A design chart to aid in the realization of a high performance APD is discussed.