利用CMOS技术实现pH-ISFET传感器集成化的设计

在对离子敏场效应晶体管(ISFET)基本结构及电学特性分析的基础上,提出了一种基于CMOS技术实现ISFET与信号处理电路集成化的设计方法.模拟仿真的结果表明,所采用的ISFET/MOSFET"互补对"结构的信号读取电路形式能够抑制"温漂"和克服"硅衬底体效应"对器件测量灵敏度的影响,是一种适用于ISFET集成设计的信号读取方式.     

集成化离子敏场效应传感器的研究进展

在介绍离子敏场效应晶体管(ISFET)传感器的应用和基本工作原理的基础上,阐述了集成化ISFET传感器的研究现状,包括ISFET敏感膜及其制造工艺与CMOS兼容性研究、集成化读出电路、多传感器集成等方面。展望了ISFET传感器的研究趋势,认为在以下方面值得探索和研究:敏感膜是把化学变量转换为电学变量的关键;高性能读出电路的研究;集ISFET、读出电路及后端信号处理电路于一体的低功耗ISFET传感器的系统集成;多功能、智能化的多传感器集成;研究集微传感器、微执行器、信号处理和控制电路、接口电路、通信系统以及电源等于一体的微机电系统(MEMS);ISFET微传感系统的数字化集成等。     

集成化离子敏场效应传感器的研究进展

在介绍离子敏场效应晶体管（ISFET）传感器的应用和基本工作原理的基础上,阐述了集成化ISFET传感器的研究现状,包括ISFET敏感膜及其制造工艺与CMOS兼容性研究、集成化读出电路、多传感器集成等方面。展望了ISFET传感器的研究趋势,认为在以下方面值得探索和研究：敏感膜是把化学变量转换为电学变量的关键;高性能读出电路的研究;集ISFET、读出电路及后端信号处理电路于一体的低功耗ISFET传感器的系统集成;多功能、智能化的多传感器集成;研究集微传感器、微执行器、信号处理和控制电路、接口电路、通信系统以及电源等于一体的微机电系统（MEMS）;ISFET微传感系统的数字化集成等。     

一种CMOS工艺离子敏场效应型晶体管的模型

采用CMOS工艺可以实现离子敏场效应型晶体管(ISFET),若在栅极氧化层之上保留多晶硅层,并通过引线使其与 外界的金属层相连作为悬浮的栅极,可实现悬浮栅结构ISFET.从ISFET的传感机理出发,根据表面基模型,利用HSPICE建 立了悬浮栅结构ISFET的物理模型.以该模型为研究对象,探讨了薄膜等效电阻、薄膜等效电...     

一种适用于ISFET读出的高精度CMOS运放设计

介绍了一种适用于ISFET读出的高精度CMOS运放设计.该运放可为ISFET提供恒定电流、电压偏置,从而便于构建读出电路并于微传感器单片集成.通过运用连续时间自调零技术,大大降低了运放的失调电压、1/f,噪声和温漂等低频噪声.该设计基于0.35/μm CMOS工艺,电源电压3.3V,运放的开环增益超过100dB,输入等效失调电压低至11/μV,总功耗仅为1.48mW.应用该运放实现的pH微传感器已通过实验验证.     

一种适用于ISFET读出的高精度CMOS运放设计

介绍了一种适用于ISFET读出的高精度CMOS运放设计.该运放可为ISFET提供恒定电流、电压偏置,从而便于构建读出电路并于微传感器单片集成.通过运用连续时间自调零技术,大大降低了运放的失调电压、1/f,噪声和温漂等低频噪声.该设计基于0.35/μm CMOS工艺,电源电压3.3V,运放的开环增益超过100dB,输入等效失调电压低至11/μV,总功耗仅为1.48mW.应用该运放实现的pH微传感器已通过实验验证.     

偏置模式可编程的ISFET集成放大器设计

生物微传感SOC系统在生命科学研究、医疗保健、环境检测等领域有广阔的应用前景,然而系统的真正实现面临着许多挑战.根据离子敏场效应管ISFET的敏感机理,研究了ISFET与其接口放大器的集成芯片,ISFET可以被提供线性和饱和两种模式下的工作条件.整个芯片包含ISFET微传感、双模式ISFET放大器,同时也集成了恒流源等,采用新加坡Char-tered半导体制造公司3.3V标准CMOS工艺流片,并成功进行了传感器芯片的pH响应测试实验.     

新型的ISFET微传感器读出电路单芯片集成研究

生化微传感集成系统是目前的研究焦点,本文以在线性区和饱和区两种模式下工作的pH-ISFET作为研究对象,提出ISFET微传感器与其信号读出电路的单芯片集成,并深入研究传感机理以及与标准CMOS兼容的敏感材料制备技术.整个芯片包含ISFET/REFET微传感差分对、双模式ISFET/REFET放大器、次级差分放大、参比电极Pt、恒流源等,采用新加坡Chartered半导体集成电路公司3.3V标准CMOS工艺流片.同时进行传感器芯片的pH响应实验测试,获得53mV/pH灵敏度.     

CMOS图像传感器中时间延迟积分的实现与优化

提出了一种在标准CMOS工艺下实现时间延迟积分(TDI)功能的电路结构,电路采用一面阵CMOS像素阵列,通过像素列曝光累积实现了TDI功能.详细分析了器件噪声和积分器噪声对电路的影响,提出了器件级噪声优化公式.电路采用SMIC 0.35 μm CMOS工艺实现.仿真结果表明,该电路能够实现TDI功能,运算放大器的等效输入噪声为36.1 μV,具有低噪声特性.     

CMOS集成电路抗闩锁策略研究

以反相器电路为例，介绍了CMOS集成电路的工艺结构；采用双端pnpn结结构模型，较为详细地分析了CMOS电路闩锁效应的形成机理；介绍了在电路版图级、工艺级和电路应用时如何采用各种有效的技术手段来避免、降低或消除闩锁的形成，这是CMOS集成电路得到广泛应用的根本保障。     

ISFET interface circuit embedded with noise rejection capability

A new constant-current voltage driver forms a bridge-type floating drain-source follower configuration applicable to the determination of H/sup +/ ion concentration. The proposed circuit maintains the ion-selective field effect transistor (ISFET) in an accurate constant drain-source voltage and current situation with good noise rejection capability. Simulation results show accurate response for ISFET applications. The presented electronic circuit can be integrated with a ISFET-based microsystem by standard CMOS technology.     

Low‐Voltage Current‐Sensing CMOS Interface Circuit for Piezo‐Resistive Pressure Sensor

A new low‐voltage CMOS interface circuit with digital output for piezo‐resistive transducer is proposed. An input current sensing configuration is used to detect change in piezo‐resistance due to applied pressure and to allow low‐voltage circuit operation. A simple 1‐bit first‐order delta‐sigma modulator is used to produce an output digital bitstream. The proposed interface circuit is realized in a 0.35 µm CMOS technology and draws less than 200 µA from a single 1.5 V power supply voltage. Simulation results show that the circuit can achieve an equivalent output resolution of 9.67 bits with less than 0.23% non‐linearity error.     

64 pH-ISFET averaging array employing global negative current feedback

The previously reported discrete ISFET using current feedback has been redesigned in a CMOS platform with an array of ISFETs to improve the performance of the single ISFET's readout. The circuit novelty is the averaging of ISFET currents generated by a cluster of 64 ISFETs with a global current feedback. Simulation results from the 0.18 μm CMOS process also indicate improvements of high signal-to-noise ratio with power consumption to early μW. As a result, it all leads to benefit biomedical applications.     

Novel high speed circuit structures for BiCMOS environment

Novel high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier are presented. A generic 0.8 μm complementary BiCMOS technology has been used in the circuit design. Circuit simulations show superior performance of the novel circuits over conventional designs. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuit and the BiCMOS sense amplifier are improved by 20, 250, and 60%, respectively. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V     

Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process

A new power-rail electrostatic discharge (ESD) clamp circuit for application in 3.3-V mixed-voltage input–output (I/O) interface is proposed and verified in a 130-nm 1-V/2.5-V CMOS process. The devices in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage nMOS/pMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V I/O interface applications. A special ESD detection circuit realized with the low-voltage devices is designed and added in the power-rail ESD clamp circuit to improve ESD robustness of ESD clamp devices by substrate-triggered technique. The experimental results verified in a 130-nm CMOS process have proven the excellent effectiveness of this new proposed power-rail ESD clamp circuit.     

A CMOS SLIC with an automatic balancing hybrid

A CMOS subscriber line interface circuit (SLIC) that has an automatic balancing hybrid facility is presented. Some of the key system aspects of line interface circuits, such as the relation between zero-loss switching and an automatic balancing hybrid circuit, power dissipation in the line circuit, and foreign voltage protection are described first. Next, details of the SLIC LSI, which comprises a dial pulse detecting circuit and and automatic balancing hybrid circuit, are described. The LSI is implemented with CMOS switched capacitor technology and is mounted on a 20-in DIL.     

An Integrated Sensor for Electrochemical Measurements

A method for the fabrication of a completely integrated solid-state electrochemical sensor which combines a minature liquid junction reference electrode with a CMOS ISFET is presented. The reference electrode is fabricated by preferentially etching silicon to form a porous silicon frit. The CMOS process provides electrical encapsulation of the ISFET. The performance of the reference electrode and CMOS ISFET as an integrated sensor is demonstrated.