通用的全帧型面阵CCD时序发生器设计方法

介绍了面阵CCD485的内部结构、工作模式,并给出了其基本驱动电路设计。然后通过对面CCD485驱动时序图的分析,分析了全帧型大面阵CCD 的正常工作、快速擦除、图像窗口输出和像元合并的驱动时序,提出了一种基于时序细分和有限状态机的通用型全帧型面阵CCD驱动时序发生器设计方法。该方法通过对CCD 驱动时序进行分组,将每一组时序的波形划分为若干个基本输出状态,这样CCD 各个工作阶段所需的驱动时序都可以由各基本状态组合出来,使用摩尔型有限状态机来描述,将时序驱动器进行了模块化设计。给出了各个模块的具体设计,使时序发生器的设计过程更加简单,最后采用Xilinx公司的Virtex-ⅡPro系列FPGA-XC2VP20、ISE软件平台,设计了CCD驱动时序发生器,并进行了波形仿真分析。输出信号完全满足485芯片的驱动时序要求,证明了该设计方法的有效性。     

高分辨率大面阵CCD相机高帧频设计及其非均匀性的校正

目前采用高分辨率全帧面阵CCD FTF5066M 作图像传感器的航拍相机帧频一般不超过1 fps,为了满足高帧频应用,文中首先介绍了全帧型面阵CCDFTF5066M 的基本驱动电路,并对其进行了改进,利用CCD 4个输出放大器进行同时输出,使最高帧频达到了3.4 fps,介绍了4 路输出时CCD驱动时序、前端处理电路、直流偏置电路、接口电路等的设计,改进后的驱动电路能满足多种航拍相机的应用要求。然后对全帧型面阵CCDFTF5066M 的非均匀性进行了分析,并建立了一种响应非均匀性检测系统。利用该系统分别对面阵CCD5066M 的4 个象限之间的非均匀性和每个像元之间的非均匀性进行了检测。在CCD 响应度为线性的基础上,提出了两点校正算法并对非均匀性进行校正。通过校正4 个象限响应灵敏度的标准偏差降低到原来的1/13。通过对鉴别率板的重新拍摄,可以看出面阵CCD 的非均匀性得到了明显的改善。     

降低CCD转移驱动电压摆幅仿真技术研究

降低CCD的转移驱动电压摆幅对于减小器件的功耗有着积极的作用.通过对CCD电荷转移过程的原理进行分析,建立了CCD转移驱动电压摆幅的仿真模型,并从势垒注入、多晶硅电极间隙、栅介质层厚度等方面进行了仿真分析,找出了影响CCD转移驱动电压摆幅的关键因素,同时利用该模型得到了降低CCD转移驱动电压摆幅的优化条件.最后采用仿真结果进行了流片验证,CCD的驱动电压摆幅由原来的7V降低到了4V,验证了仿真结果的有效性.     

支持像移补偿功能面阵CCD相机驱动电路系统

为了设计一种支持电子式像移补偿功能的高帧频大面阵CCD驱动电路,满足像移补偿功能.论文首先给出了大面阵CCDFTF5066M的基本驱动电路,然后在其基础上通过增加一个像移补偿时序发生器与主时序发生器SAA8103配合工作来实现电子像移补偿,给出了像移补偿发生器内部设计结构,所增加的像移补偿时序发生器只用于产生曝光期间所需的几个垂直转移驱动时序和转发SAA8103 产生的时序信号.选择了FPGA作为像移补偿时序发生器,并且进行了时序仿真.最后对设计的驱动电路进行了室内像移补偿实验验证,取得了很好的补偿效果,该驱动电路系统支持最大帧频可达2.7 F/s,信噪比达到了66 dB.该驱动电路能方便地选择输出通道数量和输出方式,使相机适用于不同的场合.     

一种亚像素级图像超分辨恢复算法

随着光学成像到光电数字成像的转变,如何提高CCD的几何分辨率,已成为研制高分辨光电成像系统亟待解决的问题.建立了半像元超分辨成像数学模型,提出了半像元的CCD几何超分辨方法.该方法将2片线阵CCD集成在同一器件中,在线阵方向上错开半个像元,同时读出时间减半,最终交织重组图像数据,以合成高分辨率图像.利用MATLAB软件对双线性插值方法及半像元成像方法进行了仿真,并定性定量地分析了2种方法的效果.结果显示：半像元方法合成图像分辨率约为低分辨率图像的2倍,且2组仿真图像中的PSNR比双线性插值图像分别高出1.486 4 dB和2.207 0 dB.该方法可以显著地减轻欠采样引起的图像模糊,且实时性优于双线性插值方法.     

高集成度多光谱TDI CCD焦平面系统

提出了一种高集成度TDI CCD焦平面系统,成功应用TDI CCD驱动单元厚膜集成模块完成了具有16路CCD信号输出、像元读出频率20 MHz的高集成度高速多光谱TDI CCD焦平面系统的研制。通过采用双通道CCD信号处理模拟前端、厚膜集成驱动单元模块、高速LVDS图像数据传输接口以及机、电、热一体化仿真设计方法,极大提高了TDI CCD焦平面系统的集成度,降低了系统互连的复杂程度。系统共有4路图像数据传输接口,单路传输能力达到1.6~2.5 Gbps,最高可实现10 Gbps的图像数据带宽,在保证高数据率的同时,提高了数据传输的抗干扰能力。阐述了系统设计方案及多光谱TDI CCD探测器工作原理,并对其中的机电集成设计、驱动单元厚膜集成技术以及高速串行传输总线等关键技术进行了分析描述。通过采用TDI CCD传函测试片对系统进行了测试,焦平面全系统调制传函平均为0.511。     

高帧频低拖尾帧转移CCD驱动技术

帧转移CCD在先进高光谱遥感技术中具有非常重要的应用价值,而拖尾问题是其在高光谱成像等高帧频应用中存在的最大障碍之一。为了减小拖尾的影响,建立了驱动器、PCB传输线及CCD内部结构一体化的驱动信号传输模型,比传统模型能更准确地预测CCD内部和外部的驱动信号波形;仿真对比了各种典型参数对CCD驱动信号波形的影响,仿真与实测结果具有很好的一致性。根据仿真结果进行了高帧频帧转移CCD驱动电路的优化设计,实现了100 ns的行转移时间,在500 fps的帧频下获得了拖尾系数小于1%的驱动效果,为进一步提高CCD的工作帧频提供了保障。     

大视场遥感相机的时间延迟积分电荷耦合器件测试系统

为了在基于多片CCD拼接的大视场遥感相机研制时挑选高性能和性能一致的CCD,提出了一种CCD性能参数测试系统。首先,介绍了该测试系统的各部分组成和功能。其次,阐述了该测试系统的核心部分CCD成像评估电路关键技术,提出了基于电荷泵的CCD时序驱动策略和闭环自动可调电压供电策略。然后,针对多片CCD拼接时主要考虑的一致性参数CCD像元响应非均匀性、盲像元、过热及过冷像元,提出了基于图像处理的CCD性能测试方法。最后,测试系统对XX-X遥感相机的17片CCD性能进行了测试。结果表明,待测的各片CCD参数性能指标均符合项目的设计要求。其中,各片CCD响应非均匀性均小于5%,响应度大于985 V/(J.cm-2),动态范围大于2 320:1。测试系统可以全面地评价待选用的各片CCD性能。     

RCC自激变换器的分析与设计

RCC是一种自激振荡式变换器,该电路只需要少量的分立元件就可以得到良好的稳压输出性能。其电路结构简单、成本低、高效可靠、可以实现多路输出。文中对RCC电路进行了小信号模型分析,设计了一种两路输出电压型驱动RCC电路,并进行了仿真验证。     

DL44型硅CCD2500元线阵图象传感器的设计考虑

本文描述了DL44型CCD2500元线阵图象传感器的设计考虑、性能参数及其实验结果。本器件的设计有以下几个主要特点:(1)新型的光敏元结构;(2)四个CCD移位寄存器;(3)奇偶光敏元的图象信号实行独立输出;(4)片内设计有采样和保持电路;(5)片内设计有产生暗信号参考电平和白信号电平以及扫描终止波形的电路。此外文中还介绍了器件驱动波形以及改进型驱动电路的设计。最后介绍奇偶图象信号的片外合拢技术。     

应用于海洋观测的TDI-CCD驱动电路的设计

面阵CCD及线阵CCD不能胜任海洋目标观测的要求,选用具有高信噪比高灵敏度的时间延迟积分CCD(Time delay integration CCD, TDI-CCD)作为 探测器并实现其驱动电路。在图像采集过程中,TDI-CCD探测器使用两个读取端口输出。 该探测器驱动电路产 生TDI-CCD和A/D的驱动时序。CCD的模拟输出信号被A/D采样,转换成可被计算机识别 的数字信号。采用FPGA作为主控芯片,产生驱动时序,接收被A/D转换过的数字信号, 并发送图像至计算机。利用相关双采样(Correlated double sampling, CDS)技术滤除TDI-CCD模 拟输出信号的相关噪声,提高信号的信噪比。现场可编程门阵列(Field programmable gate array, FPGA)代码在ISE14.7下进行仿真,实验表明,研制的TDI-CCD驱动电路能够产生CCD要求的驱动时序。     

A generic low-noise CMOS readout interface for 64?×?64 imaging array with on-chip ADC

This paper presents a low-noise and high dynamic-range CMOS readout-IC (ROIC) for a 64?×?64 array of opto-electrical sensors. The readout chain comprises a pixel preamplifier array, correlated-double-sampling based switched-capacitor gain blocks, class-AB output buffer for driving off-chip loads and a 12-bit pipeline ADC for on-chip digitization. The pixel preamplifiers array, occupying an area of 30???m?×?30???m per pixel, can either be hybridized to a separate IR or UV sensor or can be used as monolithic visible-light active CMOS pixel-array after exposing (by etching the pad) the embedded photodiode under the bonding pads. The ROIC is designed and fabricated in 0.25???m 1P/5?M CMOS technology with 5?mm?×?5?mm of total dimensions. The integrated readout chain, in integrate-then-read mode, demonstrates a dynamic range of 72?dB for electrically emulated sensor currents from 25?pA to 100?nA. It can support a frame rate of 700?fps, with single fully-differential analog as well as 12-bit digital output, at 10?MHz while consuming 17?mW with on-chip biases.     

A 16 384-bit high-density CCD memory

A 16 384-bit charge-coupled device (CCD) memory has been developed for mass storage memory system application where moderate latency, high data rate and low system cost are required. The chip measures only 3.45 × 4.29 mm²(136 × 169 mil²), fits a standard 16-pin package, and is organized as four separate shift registers of 4096 bits, each with its own data input and data output terminals. A two-level polysilicon gate n-channel process was used for device fabrication. A condensed serial-parallel-serial (CSPS) structure was found to provide the highest packing density. Only two external clocks are required driving capacitances of 60 pF each at one-half the data transfer rate. Operations at data rates of 100 kHz to 10 MHz have been demonstrated experimentally, the on-chip power dissipation at 10 MHz being less than 20 µW/bit.     

A Multiple-Gate CCD-Photodiode Sensor Element for Imaging Arrays

The addition of barrier and storage gates between the photodiodes and transfer gates of a CCD imaging array provides improved and versatile operating characteristics compared with present silicon scanners. An experimental scanner, made with multiple-gate photoelements, has new functional capabilities which result from the on-chip structure. These include exposure control in real-time which can compensate for temporal illumination variations during the integration cycle, linearization of the output signal with respect to light intensity, and adaptive level setting to normalize the output based on the whitest portion of the image. Complete charge transfer into the shift register is achieved at reduced shift-register voltages. The use of photodiodes and the absence of polysilicon in the photosensitive region improve spectral response and overall sensitivity. A sixteen element 4-phase, 2-level polysilicon CCD imager was designed, fabricated, and used to test the improved photoelement structure.     

A multiple-gate CCD-photodiode sensor element for imaging arrays

The addition of barrier and storage gates between the photodiodes and transfer gates of a CCD imaging array provides improved and versatile operating characteristics compared with present silicon scanners. An experimental scanner, made with multiple-gate photoelements, has new functional capabilities which result from the on-chip structure. These include exposure control in real-time which can compensate for temporal illumination variations during the integration cycle, linearization of the output signal with respect to light intensity, and adaptive level setting to normalize the output based on the whitest portion of the image. Complete charge transfer into the shift register is achieved at reduced shift-register voltages. The use of photodiodes and the absence of polysilicon in the photosensitive region improve spectral response and overall sensitivity. A sixteen element 4-phase, 2-level polysilicon CCD imager was designed, fabricated, and used to test the improved photoelement structure.     

An all-band TV tuner IC with 10-GHz 100-V mixed analog/digital Sibipolar technology

An all-band TV tuner IC with an on-chip PLL and a high-voltage output stage is developed. The use of a self-aligned bipolar technology called high-voltage compatible sidewall base contact structure (HV-SICOS) allows the integration of 1-GHz analog circuits, 1-GHz low-power ECL-I²L PLL circuits, and a 0.5- to 30-V tuning diode bias current on the same chip. The analog block has a VCO and mixer pair for the VHF/CATV and another pair for the UHF bands, a UHF input amplifier, an IF amplifier, and a VCO signal switching circuit. To suppress the digital noise level for mixed analog/digital mode operation, the PLL is constructed with high-speed ECL circuits for divide-by-four and dual modulus prescalers, and low-power I²L circuits. An isolation area is placed between the analog and digital blocks. Conversion gain of 24 dB for VHF/CATV and 33 dB for UHF, a noise figure of 10 dB, and 1% cross modulation of 95 dB-μV are obtained. This IC operates with a total power dissipation of 200 mW on a 3-mm×4-mm chip     

Programmable CCD correlator

A programmable CCD tapped delay line, useful in radar and communications signal processors, is described. The 64-stage CCD, tapped at each stage, has been operated as a binary-weighted analog correlator, and as a bandpass filter. The CCD is a shallow, buried, n-channel device while the on-chip logic required for reference code input and storage is NMOS. Test results indicate near-theoretical peak-to-sidelobe ratio for 64-bit codes, good linearity, and high-speed operation (in excess of 15 MHz). Differential subtraction of summed signal currents on-chip has been demonstrated.     

不同源漏掺杂方式对CCD放大器的影响

通过对CCD片上放大器不同源漏掺杂条件、方块电阻、接触电阻、有效沟道长度的分析研究,确定了源漏工艺条件为磷离子注入能量100keV、剂量5×1015 cm-2。分析了扩散、离子注入源漏掺杂对放大器直流输出的影响,结果表明,当宽长比为4/1时,注入源漏掺杂制作的放大器直流输出与仿真值差异为0.28V,优于扩散工艺。     

多抽头EMCCD相机时序控制及像元合并技术

高速、高灵敏度相机在自适应光学系统中可以对波前误差进行实时测量,为大型地基望远镜提供接近衍射极限的目标图像。多抽头电子倍增电荷耦合器件(EMCCD)相机是自适应光学波前探测的最佳选择之一,基于8抽头的CCD220设计了2000f/s级高速、高精度、多路同步时序发生器,并通过时序控制的方法在CCD器件上实现了多种像元合并,进一步将相机帧频提高到3500f/s(2×2合并)和5700f/s(4×4合并),并能对相机感兴趣区域进行控制。时序发生器的步进精度可达到2.5ns,输出的各路驱动信号的相位抖动可达200ps以下。     

Operation and characteristics of a CLIP imager

An interline-transfer CCD imager with 580 × 475 elements for the ⅔-in optical format is described. The imager employs the clock-line-isolated photodiode (CLIP) structure that eliminates the field oxide and the field ion implant by exploiting the clock lines which so far have been placed only to carry the driving pulses. In spite of the elimination of such channel stops, it can operate not only in a frame integration mode but in a field integration mode. A saturation current of 170 nA and a horizontal resolution of 340 TV lines were obtained in both the modes. The vertical resolution was 570 TV lines in the frame-integration mode, while over 400 TV lines in the field-integration mode.