基于子波相关算法的红外图像点目标检测

红外图像中点目标的检测技术是近年来信息处理研究的热点和难点之一，目标在图像中的表现为点状，且信噪比低，目标被噪声（杂波）淹没，现结合前人的一些检测算法，按照背景信号和噪声在相邻的子带间所表现出的不同相关性这一特点来进行背景信号、噪声的分析，提出了基于子波相关算法的点目标的检测方法，并对其进行了仿真和软件编程，结果表明这种算法具有很好的检测能力。     

基于子波相关算法的红外图像点目标检测

红外图像中点目标的检测技术是近年来信息处理研究的热点和难点之一^[1]。目标在图像中表现为点状，且信噪比低，目标被噪声（杂波）淹没。文中结合前人的一些检测算法，按照背景信号和噪声在相邻的子带间所表现出的不同相关性这一特点来进行背景信号、噪声的分析。提出了基于子波相关算法的点目标的检测方法，并对其进行了仿真和软件编程。结果表明这种算法具有很好的检测能力。     

基于子波相关算法的红外图像点目标检测( 英文)

红外图像中点目标的检测技术是近年来信息处理研究的热点和难点之一。目标在图像中的表现为点状 ,且信噪比低 ,目标被噪声 (杂波 )淹没。现结合前人的一些检测算法 ,按照背景信号和噪声在相邻的子带间所表现出的不同相关性这一特点来进行背景信号、噪声的分析 ,提出了基于子波相关算法的点目标的检测方法 ,并对其进行了仿真和软件编程。结果表明这种算法具有很好的检测能力     

低信噪比下两种点目标检测算法的研究

红外图像中点目标检测技术是近年来信息处理研究的热点和难点之一。当红外图像传感器和目标之间距离很远时,目标在焦平面上成像面积很小,一般不超过探测器像元的大小,因此目标在图像中表现为点目标,且信噪比极低,目标被噪声（杂波）所淹没,给目标的检测带来了极大的困难。这一领域,前人已经进行了大量的研究工作,并提出了一些检测算法。文中也研究设计了两种红外图像点目标检测算法,并对其进行了计算机仿真实验和分析,结果表明这两种算法具有较好的检测能力。     

基于多向背景预测的红外弱小目标检测

杂波背景中的弱小目标检测是红外图像处理中的一个重要问题。普通的二维滤波背景预测方法可以用来检测图像中的小目标,但是也存在对复杂场景的适应性差,杂波边缘虚警高的问题。通过分析二维最小均方滤波背景预测算法的方向特性,在对图像四邻域滤波残差进行像素级加权融合后,得到了一种基于多方向融合自适应滤波背景预测的弱小目标检测方法。对构造图像和实际红外云杂波场景中的小目标检测仿真表明,该方法对不同背景适应性较强,在保持目标检测概率的同时显著抑制了杂波边缘虚警,有效提高了杂波背景中小目标的检测性能。      

旋转均值滤波用于提高红外点目标图像信噪比

当距离红外传感器很远时，目标在红外图像中表现为点目标。充分利用点目标，背景杂波及噪声在空间域中的表现形式，并结合均值滤波滤除噪声的特性，提出了一种新的滤波方法——旋转均值滤波法。将此算法运用在信噪比不大于3的红外点目标图像中，实现了背景抑制，突出目标以及提高信噪比作用，并能够满足实时处理的要求。     

红外小目标时域检测算法研究

为了解决红外小目标检测问题,提出了时域红外小目标检测方法.在图像序列中背景像素、目标像素以及杂波像素的时域差分模型基础上提出了红外小目标时域检测算法,算法共分为两步:相关检测和广义似然比检测.经过相关检测后,图像序列中的噪声几乎完全被门限所抑制,只有极少数噪声像素、全部目标像素和一小部分杂波像素可以通过相关检测门限.为了进一步从通过相关检测门限的像素中检测出目标,又提出了一种新的广义似然比检测方法.这种经过改进的广义似然比检测能够进一步抑制噪声和杂波,提高检测的性能.分析表明,时域目标检测算法能够以很高的检测概率和很低的虚警概率完成目标的检测,实验方法也证实红外小目标时域检测算法具有很好的性能.     

基于多尺度反锐化掩模的红外图像云层背景抑制

为检测强云杂波背景中的红外弱小运动目标,结合反锐化掩模理论,提出了一种基于曲线波变换的多尺度反锐化掩模红外图像云层背景抑制新方法。首先,根据红外目标和背景杂波的特性,采用二代曲线波变换对图像进行多尺度、多方向分解,提取图像的多尺度和方向细节特征,然后,根据目标和背景杂波子带系数的差异,通过应用反锐化掩模理论调整分解后的各子带系数,从而将红外图像中弱小目标信号和背景杂波分离,达到抑制背,景的目的。实验结果显示,与最大中值（MMed）和二维最小均方误差（TDLMS）方法比较,该方法对信杂比较低的红外弱小目标复杂云层背景从主观视觉和数值指标都具有良好抑制效果。     

红外空域弱小目标探测系统中恒虚警技术研究

对空域中弱小目标的探测是红外成像防御与制导的关键技术。由于空域中弱小目标距离较远,在红外探测器上呈现为无纹理特征的弱小点。由于红外探测器噪声与视场中杂波干扰,很难将目标从红外图像中提取出来。在红外空域弱小目标探测系统中,虚警率与探测率是一对矛盾的概念。针对这一问题提出了一种基于杂波模型估计理论的恒虚警(CFAR)检测技术。该CFAR技术是建立在对红外图像背景杂波分析建模的基础上,根据Neyman-Pearson准则设计CFAR检测器,实现在恒定虚警的前提下最大化追求系统的探测率,以此提高红外空域弱小目标探测系统的探测距离和目标识别能力。     

基于联合方向梯度和均值对比度的红外弱小目标检测方法

针对小目标在整幅图像中占比很低,且目标周围存在大量杂波,提出了一种基于联合方向梯度（Associated Directional Gradient,ADG）和均值对比度（Mean Contrast,MC）的红外弱小目标检测算法。该算法由两个模块组成：ADG利用红外弱小目标的高斯分布模型,将单一方向的梯度与一个相邻方向上的梯度相加组成新的联合梯度特征,增强真实目标、抑制背景杂波的同时能够消除高亮边缘对目标检测效果的影响;MC融入方向信息来计算目标的多方向对比度,选用多方向对比度的最小值抑制结构噪声,并将均值滤波的思想引入对比度的计算,抑制背景中的孤立噪声,进一步降低检测的虚警率。在实际红外图像上的实验结果表明,该算法在增强目标信噪比和抑制背景噪声方面,能够取得较好效果。     

A novel low-temperature method of SiO2 film deposition forMOSFET applications

Silicon dioxide dielectric films were deposited at low temperatures (250–300°) using a novel plasma enhanced MO-CVD process. In this process, the substrate was kept remote from the plasma region and the deposition of the film was achieved at low pressure (0.8-1.0 Torr) and low dc plasma power (0.3 W· cm⁻²). Films deposited using tetraethyloxysilane (TEOS) and nitrous oxide (N₂O) as reactant material had, under optimum deposition conditions, resistivities of ≥ 10¹⁵ ohm-cm, a refractive index of 1.46, a dielectric constant of 3.98 and a breakdown field strength ≥ 5x 10₆ V·cm⁻¹. AES and SIMS analysis indicated that the films were of high purity and were stoichiometric with no metallic silicon present. MOS-capacitors fabricated on Si-substrates showed no hysteresis and no frequency dispersion of capacitance in the accumulation region. An interface state density in the range of 10¹¹ cm⁻²eV⁻¹ was achieved for these MOS devices using our deposited SiO₂dielectric films.     

Carrier transport and related phenomena in MOS devices

Silicon-based devices are currently the most attractive group because they are functioning at room temperature and can be easily integrated into conventional silicon microelectronics. There are many models and simulation programs available to compute CV curves with quantum correction [Choi C-H, Wu Y, Goo JS, Yu Z, Dutton RW. IEEE Trans on Electron Devi 2000; 47(10): 1843; Croci S, Plossu C, Burignat S. J Mater Sci Mater Electron 2003; 14: 311; Soliman L, Duval E, Benzohra M, Lheurette E, Ketata K, Ketata M. Mater Sci Semicond Process 2001; 4: 163]. This work deals with the simulation of electron transfer through SiO₂ barrier of metal–oxide–semiconductor structure (MOS). The carrier density is given by a self consistent resolution of Schrödinger and Poisson equations and then the MOS capacitance is deduced and compared with results available in literature. As it is well known, the MOS capacitance–voltage profiling provides a simple determination of structure parameters. The extracted tunnel oxide thickness and substrate doping are compared with those used in the simulation. For the purpose to investigate the electron tunnelling through the barrier, we have used the transfer matrix approach. Using I–V simulations, we have shown that the traps in SiO₂ matrix have a drastic influence on electron tunnelling through the barrier. The trap-assisted contribution to the tunnelling current is included in many models [Maserjian J, Zamani N. J Appl Phys 1982; 53(1): 559; Houssa M, Stesmans A, Heyns MM. Semicond Sci Technol 2001; 16: 427; Aziz A, Kassmi K, Kassmi Ka, Olivie F. Semicond Sci Technol 2004; 19: 877; Wu You-Lin, Lin Shi-Tin. IEEE Trans Dev Mater Reliab 2006; 6(1): 75; Larcher L. IEEE Trans Electron Dev 2003; 50(5): 1246]; this is the basis for the interpretation of stress induced leakage current (SILC) and breakdown events. Memory effect becomes typical for this structure. We have studied the I–V dependence with trap parameters.     

Analytic approximation of the jitter incurred by CBR traffics in IP networks

In this paper, an analytic approximation is derived for the end-to-end delay-jitter incurred by a periodic traffic with constant packet size. The single node case is considered first. It is assumed that the periodic traffic is multiplexed with a background packet stream under the FCFS service discipline. The processes governing the packet arrivals and the packet sizes of the background traffic are assumed to be general renewal processes. A very simple analytical approximation is derived and its accuracy is assessed by means of event-driven simulations. This approximation is then extended to the multiple node case yielding a simple analytical approximation of the end-to-end jitter. This approximation is shown to be fairly accurate in the light to moderate traffic conditions typically encountered in IP core networks.     

Low-Power FPGA-Implementation of <Emphasis Type="Italic">atan</Emphasis>(<Emphasis Type="Italic">Y</Emphasis>/<Emphasis Type="Italic">X</Emphasis>) Using Look-Up Table Methods for Communication Applications

This paper presents an architecture for the computation of the atan(Y/X) operation suitable for broadband communication applications where a throughput of 20 MHz is required. The architecture takes advantage of embedded hard-cores of the FPGA device to achieve lower power consumption with respect to an atan(Y/X) operator based on CORDIC algorithm or conventional LUT-based methods. The proposed architecture can compute the atan(Y/X) with a latency of two clock cycles and its power consumption is 49% lower than a CORDIC or 46% lower than multipartite approach.

New op-amp-RC to G m -C transformation method

A new transformation method is proposed and used to transform op-amp-RC circuits to G _m -C ones with only grounded capacitors. The proposed method enables the generation of high-performance G _m -C filters that benefit from the advantages of good and well-known op-amp-RC structures and at the same time feature electronic tunability, high frequency capability and monolithic integration ability. An attractive feature of the proposed method is that it results in G _m -C structures with only grounded capacitors in spite of the presence of floating capacitors in the original op-amp-RC circuits. Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964, the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA, U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering. He is currently Professor Electronics and Communications Engineering Department, Cairo University, Egypt. From September 1997–September 2003, Dr. Soliman served as Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985–1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987–1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo. He was a visiting scholar at Bochum University, Germany (Summer 1985) and with the Technical University of Wien, Austria (Summer 1987). In November 2005, Dr. Soliman gave a lecture at Nanyang Technological University, Singapore. Dr. Soliman was also invited to visit Taiwan and gave lectures at Chung Yuan Christian University and at National Central University of Taiwan. In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr. Soliman is a Member of the Editorial Board of the IEE Proceedings Circuits, Devices and Systems. Dr. Soliman is a Member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Dr. Soliman served as Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters) from December 2001 to December 2003 and is Associate Editor of the Journal of Circuits, Systems and Signal Processing from January 2004–Now.     

Comparison of <Emphasis Type="Italic">p</Emphasis>-cycles and <Emphasis Type="Italic">p</Emphasis>-trees in a unified mathematical framework

As high-speed networks grow in capacity, network protection becomes increasingly important. Recently, following interest in p-cycle protection, the related concept of p-trees has also been studied. In one line of work, a so-called “hierarchical tree” approach is studied and compared to p-cycles on some points. Some of the qualitative conclusions drawn, however, apply only to p-cycle designs consisting of a single Hamiltonian p-cycle. There are other confounding factors in the comparison between the two, such as the fact that, while the tree-based approach is not 100% restorable, p-cycles are. The tree and p-cycle networks are also designed by highly dissimilar methods. In addition, the claims regarding hierarchical trees seem to contradict earlier work, which found pre-planned trees to be significantly less capacity-efficient than p-cycles. These contradictory findings need to be resolved; a correct understanding of how these two architectures rank in terms of capacity efficiency is a basic issue of network science in this field. We therefore revisit the question in a definitive and novel way in which a unified optimal design framework compares minimum capacity, 100% restorable p-tree and p-cycle network designs. Results confirm the significantly higher capacity efficiency of p-cycles. Supporting discussion provides intuitive appreciation of why this is so, and the unified design framework contributes a further theoretical appreciation of how pre-planned trees and pre-connected cycles are related. In a novel further experiment we use the common optimal design model to study p-cycle/p-tree hybrid designs. This experiment answers the question “To what extent can a selection of trees compliment a cycle-based design, or vice-versa?” The results demonstrate the intrinsic merit of cycles over trees for pre-planned protection.     

Stress in “cathodic” plasma oxides as a function of processing parameters

Stress in SiO₂ films grown via a “cathodic” plasma oxidation process has been examined as a function of growth and processing conditions. The total stress for oxides grown at 350° C in either 85% Ar/15%O₂ or 100% O₂ ambients at 700 W, 4 MHz, and a total pressure of 80 mTorr was found to be identical. It was observed that annealing these oxides for 24 hr at 700° C in an ultra-pure oxygen ambient did not have any effect on the electrical properties, but that the stress did increase slightly. Electrical properties were measured on MOS capacitors, specifically focusing on net fixed oxide charge and breakdown strength. In addition, both as-grown and annealed samples were subjected to 8.5 × 10⁶ rad(SiO₂) Al K_α ionizing radiation to simulate exposure to X-ray lithography. Notwithstanding the generation of a large areal density of net coulombic charge in the insulator, the presence of these defects did not cause a measurable change in the interfacial stress level. Surprisingly, it was found that about 16% of the wafers plastically deformed during oxide growth at 350° C and about 35% of the wafers were found to be deformed after annealing of the oxides at 700° C. Dry, thermal oxides grown at 700° C were seen to possess similar electrical properties but exhibited a higher stress than the plasma oxides.     

dV/dt对IPM中IGBT栅极电路的影响分析

The effect of dV/dt on the IGBT gate circuit in IPM is analyzed both by simulation and experiment.It is shown that a voltage slope applied across the collector-emitter terminals of the IGBT can induce a gate voltage spike through the feedback action of the parasitic capacitances of the IGBT.The dV/dt rate,gate-collector capacitance, gate-emitter capacitance and gate resistance have a direct influence on this voltage spike.The device with a higher dV/dt rate,gate-collector capacitance,gate resistance and lower gate-emitter capacitance is more prone to dV/dt induced self turn-on.By optimizing these parameters,the dV/dt induced voltage spike can be effectively controlled.     

Comments on “Reliability and component importance of a consecutive-k-out-of-n system” by Zuo

Zuo claimed that the comparison of Birnbaum importance between two components for a consecutive-k-out-of-n:G system is the same as that for the F-system. We show that this is not the case and give a correct relation between the two systems.     

Design of Nonlinear CA Based TPG Without Prohibited Pattern Set In Linear Time

This paper reports an efficient BIST solution for VLSI circuits. The solution is based on an on-chip Pseudo-Random Pattern Generator (PRPG) for the CUTs (Circuit Under Test) of a VLSI chip that may be accessed through a full or partial scan path. The test solution guarantees non-issuance of the test patterns declared prohibited to a CUT. An n-bit Test Pattern Generator (TPG), for any arbitrary value of n, has been designed in linear time around the nonlinear Cellular Automata (CA). Experimental results confirm the enhanced pseudo-random quality of the generated test patterns, avoiding prohibited patterns due to application of nonlinear CA.This revised version was published online in March 2005 with corrections to the cover date.