Impedance characteristics of power distribution grids in nanoscale integrated circuits

The essential design characteristic of nanoscale integrated circuits is increased interconnect complexity. Conductors at different levels of the interconnect hierarchy have highly different physical and, consequently, electrical characteristics. These interconnect lines also exhibit inductive behavior due to enhanced switching speed of nanoscale devices, making interconnect design and analysis difficult. The design of robust and area efficient power distribution networks for high-speed integrated circuits has therefore become a challenging task. The impedance characteristics of multilayer power distribution grids and the relevant design implications are the subject of this paper. The power distribution network spans many layers of interconnect with disparate electrical properties. Unlike single-layer grids, the electrical characteristics of multilayer grids vary significantly with frequency. As the frequency increases, a large share of the current flow is transfered from the low-resistance upper layers to the low-inductance lower layers. The inductance of a multilayer grid therefore decreases with frequency, while the resistance increases with frequency. The lower layers of multilayer power grids provide a low-inductance current path, significantly reducing the grid impedance at high frequencies. Multilayer power distribution grids extend to the lower interconnect layers, exhibiting superior high-frequency impedance characteristics as compared to power distribution grids built exclusively within the upper, low-resistance metal layers. A significant share of metal resources to distribute the global power should therefore be allocated to the lower metal layers. An analytic model is also presented to determine the impedance characteristics of a multilayer grid from the inductive and resistive properties of the comprising individual grid layers.     

新型的3D堆叠封装制备工艺及其实验测试

为了满足超大规模集成电路(VLSI)芯片高性能、多功能、小尺寸和低功耗的需求,采用了一种基于贯穿硅通孔(TSV)技术的3D堆叠式封装模型.先用深反应离子刻蚀法(DRIE)形成通孔,然后利用离子化金属电浆(IMP)溅镀法填充通孔,最后用Cu/Sn混合凸点互连芯片和基板,从而形成了3D堆叠式封装的制备工艺样本.对该样本的接触电阻进行了实验测试,结果表明,100 μm2Cu/Sn混合凸点接触电阻约为6.7 mΩ高90 μm的斜通孔电阻在20～30mΩ该模型在高达10 GHz的频率下具有良好的机械和电气性能.     

Modeling and optimization of via formation in dielectrics by laser ablation using neural networks and genetic algorithms

Laser ablation is an effective process for forming vias in dielectric layers during the fabrication of multilayer substrates in microsystems packaging. In this paper, vias with diameters of 10-50 /spl mu/m are ablated in DuPont Kapton E polyimide using an Anvik HexScan 2150 SXE excimer laser operating at 308 nm. A statistical experiment employing a 2/sup 5-1/ fractional factorial design is conducted to determine the significance of laser fluence, shot frequency, number of pulses, and the vertical and horizontal positions of the debris removal system on the ablated thickness of the dielectric, top via diameter, via wall angle, and via resistance. Resistance measurements on metal deposited in ablated vias are performed to characterize via quality. Neural networks (NNs) are trained using the error back-propagation algorithm to model the ablation process using the measurement data collected from the experiment. Genetic algorithms are then utilized in conjunction with the NN models to derive optimized process recipes for achieving target responses. The recipes identified are subsequently verified by experiment. These optimized recipes are found to improve ablation results by as much as 40% for the ablated film thickness, 30% for via diameter, 9% for via wall angle, and more than 100% for via resistance.     

Optimization of via distribution and stacked via in multi-layered P/G networks

The usage of via stack was not carefully studied in previous multi-layered P/G (Power/Ground) network designs. However, with feature size scaling down, the resistance of via is increasing quickly and their influence on voltage drop of P/G networks has become obvious. In this paper, two optimization techniques for via placement are proposed, which are proved to be helpful in reducing on die voltage drop. Firstly, an efficient heuristic algorithm based on sensitivity analysis is presented to optimize via distribution in early design stage. Compared with even distribution design strategies, averagely the heuristic algorithm can reduce the worst voltage drop by 8.43% without adding more vias. Secondly, experiments demonstrated that using stacked vias in nonadjacent layers is powerful in eliminating “hot” areas which suffer from large voltage drop. Based on this observation, a heuristic algorithm is developed to further reduce the worst voltage drop. Experiments show that voltage drop distribution can be well optimized by combining these two strategies together.     

Modeling of multilayered power distribution planes using transmission matrix method

This paper presents a method for analyzing multilayered rectangular and irregular shaped power distribution planes in the frequency and time domain. The analysis includes the effect of vias on the power distribution network. The planes are modeled using a two dimensional array of distributed RLCG circuit elements. Planes are connected in parallel using vias, which are modeled as self and mutual inductors. For the computation of the power distribution impedances at specific points in the network, a multiinput and multioutput transmission matrix method has been used. This is much faster than Spice and requires smaller memory. Using the transmission matrix method, via effects and the effects of multiple rectangular power/ground plane pairs without and with decoupling capacitors have been analyzed for realistic structures.     

Selectively deposited nickel film for via filling

A selective deposition process is used to fill vias in VLSI multilevel interconnection. Ni film is chosen as the via-filling material because of its compatibility with the underlying Al film. The vias are filled with a thin Pd film first and a thick Ni film. The deposited Ni film is uniform and smooth in the via regions. This film is not attacked by the plasma etch used in subsequent Al patterning; therefore, the design rule of overlapping the second metal on vias can be relaxed. The specific via resistance of this process is 4×10 ^-9Ω-cm². The via resistance increases about 30% after an exposure to 450°C for 8 h     

A copper/polyimide Metal-base packaging technology

A unique substrate MCPM (Mitsubishi Copper Polyimide Metal-base) technology has been developed by applying our basic copper/polyimide technology.¹ This new substrate technology MCPM is suited for a high-density, multi-layer, multi-chip, high-power module/package, such as used for a computer. The new MCPM was processed using a copper metal base (110 × 110 mm), full copper system (all layers) with 50-μm fine lines. As for pad metallizations for the IC assembly, we evaluated both Ni/Au for chip and wire ICs and solder for TAB ICs. The total number of assembled ICs is 25. To improve the thermal dispersion, copper thermal vias are simultaneously formed by electro-plating. This thermal via is located between the IC chip and copper metal base, and promotes heat dispersion. We employed one large thermal via (4.5 mm^?) and four small vias (1.0 mm^?) for each IC pad. The effect of thermal vias and/or base metal is simulated by a computer analysis and compared with an alumina base substrate. The results show that the thermal vias are effective at lowering the temperature difference between the IC and base substrate, and also lowering the temperature rise of the IC chip. We also evaluated the substrate’s reliability by adhesion test, pressure cooker test, etc.     

A Semi-Analytical Approach for System-Level Electrical Modeling of Electronic Packages With Large Number of Vias

This paper presents a semi-analytical approach for electrical performance modeling of complex electronic packages with multiple power/ground planes and large number of vias. The method is based on the modal expansion technique and the method of moments. For the inner package domain with multiple power/ground planes and many vias, the modal expansion method is employed to compute the electromagnetic fields from which the multiport network parameters, e.g., the admittance matrix can be easily obtained. For the top/bottom domain of signal layers, the moment method is used to extract the equivalent resistance, inductance, capacitance, and conductance (RLCG) parameters. The equivalent circuit for the entire package is then generated by combining the results for both package domains. The equivalent circuit can be used in a SPICE-like simulator to study the signal and power integrity of an electronic package. Numerical examples demonstrate that the new approach is able to provide fast yet accurate signal and power integrity analysis of multilayered electronic packages.     

A new failure mechanism by corrosion of tungsten in a tungsten plug process

The tungsten filled via plug process is commonly used in sub-half micron CMOS process technologies. As process technologies shrink beyond the 0.25 μm generation, the metal overlap over the via also reduces. This results in vias not fully covered by the overlying interconnect lines. In the evaluation of such structures, we have observed a new failure mechanism resulting in completely unfilled vias due to electrochemical corrosion accelerated by a positive charge on specific structures. This positive charge is collected by the metal connected to the via during metal plasma etch processing and results in electro-chemical corrosion during a subsequent solvent strip process. The charge collection is found to be dependent on the geometry of the test structure. The corrosion rate is dependent on the amount of charge and the solvent pH. Methods to limit this corrosion are discussed.     

Error analysis leading to design criteria for transmission linemodel characterization of ohmic contacts

The transmission line model (TLM) is a standard method for planar specific contact resistance measurement. Although widely used, the accuracy of a measurement is typically not stated. In addition to contributions from random errors, there can be substantial contributions from systematic errors in typical TLM measurements. In this paper, we develop an analytical model for the experimental uncertainty from the fundamental TLM expressions in order to understand and calculate the uncertainty associated with the specific contact resistance and sheet resistance derived by the TLM method. The experimental uncertainties in measured resistances, together with the pad width and pad spacing, are the dominant contributions to the total uncertainty. Analytical expressions for relative random and systematic uncertainties in contact resistance and sheet resistance are developed in terms of the error contributions and the parameters of the TLM geometry. Expressions for minimum uncertainty, with associated optimum widths and sheet resistances, serve as a basis for the design of TLM structures with minimum uncertainty. The model quantifies the increase in relative uncertainty associated with decreasing contact resistance. Simulations of uncertainty under various sheet resistance, contact resistance, and pad width are implemented and uncertainties are calculated for realistic data sets     

A simple metal-semiconductor substructure for the advanced thermo-mechanical numerical modeling of the power integrated circuits

The metallization of double-diffused metal-oxide semiconductor (DMOS) power devices, which operate under fast thermal cycling (FTC), undergoes thermal induced plastic metal deformation (TPMD). The design of the metallization has a significant impact on the device lifetime and thus requires a thorough understanding of the temperature, stress and strain distribution. A simple three-dimensional (3D) transistor substructure which is commonly found in various high integration Bipolar-CMOS-DMOS (BCD) technologies is analysed. The thermomechanical behaviour is studied with the finite element method (FEM) for investigation of two potential failure mechanisms: delamination of power metal and accumulation of plastic deformation in signal metallization layer (which leads to inter-metal dielectric cracking). These failure mechanisms are analysed on two versions of the structure: the first one has only signal and power metal lines and the second one has vias, in addition to the signal and power metal lines. The target of the paper is to propose an efficient finite element analysis (FEA) model that can be used for a qualitative assessment of thermo-mechanical phenomena in the metal system of high integration BCD technologies.     

Compact physical models for multilevel interconnect crosstalk in gigascale integration (GSI)

For the first time, compact physical models are derived for crosstalk noise of coplanar resistance-inductance-capacitance lines in a gigascale integration (GSI) chip that simultaneously consider far and near aggressors in both the same metal level and distant metal levels. Since both the amplitude and duration of noise are important, the noise voltage-time integral can be defined as a figure-of-merit for crosstalk, and it is shown that this integral attains its maximum at the length at which the interconnect resistance becomes equal to twice the characteristic impedance. It is also shown that crosstalk can be prohibitively large if interconnects have small resistances. There is, therefore, a tradeoff between interconnect latency and crosstalk. The compact models are finally used to calculate the crosstalk noise voltage for the case that wire width is optimized by simultaneously maximizing data flux density and minimizing latency. It has been proven that by utilizing the optimal wire width for signal interconnects and twice of that for power and ground lines, the worst case peak crosstalk noise voltage becomes smaller than 0.25 V/sub dd/ for all generations of technology.     

Reliability evaluation of tungsten donut-via as an element of the highly robust metallization

The typical via layout in CMOS technology with AlCu-metallizations and tungsten via is cylindrical. Common vias have a size as small as possible in the related process. More challenging application, temperature and mission profiles require higher robustness of a metallization [1,2]. Via arrays of small common vias are in use to the transfer of higher currents [3]. But the typical via array layout is not the best layout for applications which are faced to high mechanical stress because via arrays metal layer connections make these parts in the stack inflexible.The developed so called highly robust metallization is optimized for applications with extended operating conditions regarding higher currents and temperatures as well as mechanical stress [4]. Donut-Vias are elements of the highly robust metallization for the interconnection of highly robust metal lines. The paper shows the layout of a Donut-Via and explains the benefits and limits of the new layout by simulation and test results.     

微波多芯片组件中垂直通孔互连的矩阵束矩量法仿真

在微波多芯片组件中,处在不同层的信号传输线是通过通孔连接在一起的。由于通孔会导致信号传输的不连续性,对信号的传输至关重要。本文采用矩阵束矩量法仿真了多层电路中通孔的散射特性,并总结了通孔几何尺寸和平行导体板间距变化时通孔的散射特性所表现出来的规律。     

Modeling solar cells with the dopant‐diffused layers treated as conductive boundaries

Modeling of transport and recombination of charge carriers in solar cells is useful for understanding and improving the device performance. We implement the fully coupled transport equations for electrons and holes into the finite‐element partial differential equation solver COMSOL . The dopant‐diffused surface regions such as junctions, floating junctions, or back surface field layers are treated as conductive boundaries of the volume in which the semiconductor equations are solved. This so‐called conductive boundary (CoBo) model characterizes diffused layers by their sheet resistances and diode saturation current densities. Both are directly experimentally accessible. The CoBo model exhibits excellent numerical stability and enables two‐dimensional simulations on a laptop. We find agreement when testing the two‐dimensional COMSOL implementation of the CoBo model for one‐dimensional devices against simulations using the code PC1D. We apply the CoBo model to elucidate how the sheet resistance of diffused vias impacts the power conversion efficiency of emitter wrap through solar cells. Copyright © 2010 John Wiley & Sons, Ltd.     

Optical and thermal properties of large-area OLED lightings with metallic grids

We investigate the effects of auxiliary metal electrodes on the optical and thermal properties of large-area (30 × 120 mm²) opaque and transparent white OLED lighting panels. Enlarging their emission area inevitably entails a non-uniform current distribution due to the limiting conductivity of transparent electrodes, causing local heat generation. To tackle it, we have used grid patterned Cr, Mo/Al/Mo, or Cu metal lines (0.15 mm in width) as auxiliary metal electrodes on an ITO anode. Among those, Cu metal grids exhibit the highest luminous efficacy with the least heat generation, and the most uniform light distribution by virtue of its lowest sheet resistance, followed by Mo/Al/Mo and then Cr metal grids. It is also found that local heat generation appears more seriously in large-area transparent OLED panels. With attempt to suppress it, we have also deposited Al metal lines (2 mm in width) on a semitransparent Al/Ag cathode by thermal evaporation, which brings in a highly uniform heat distribution. Furthermore, we study the effect of the shape of the light-emitting area on the luminance and heat distributions. A round-shaped OLED panel with a hexagonal metal grid exhibits highly homogeneous luminance and surface temperature distributions.     

A study of the effect of post-metal etch wet cleaning processes and silicon oxynitride film on charge induced corrosion of tungsten vias

We report the experimental study of prevention of charge induced corrosion of tungsten vias after metal etch using wet chemical solutions and silicon oxynitride (SiON) shielding film. It was found that one of the solutions could effectively prevent corrosion of tungsten vias and leave essentially no polymer residue on metal lines. The performance of other solutions is poor due to the formation of polymer residues or sidewall erosion on metal lines. We have demonstrated that the combination of wet chemical treatment with SiON as the dielectric charge shielding film was as effective as other standard methods for preventing corrosion of tungsten vias. It was also found that SiON has strong impacts on chamber wall conditions and metal line profile.     

Power distribution techniques for VLSI circuits

The onchip power distribution problem for highly scaled technologies is investigated. Metal migration and line resistance problems as well as ways to optimize multilayer metal technology for low resistance, low current density, and maximum wirability are also investigated. Fundamental lower limits and the limiting factors of the power-line current density and the voltage drop are studied. Tradeoffs between interconnect wirability and power distribution space are examined. Power routing schemes, as well as the optical number of metal layers and the optimal thickness of each layer, are examined. The results indicate that orders of magnitude improvements in current density and resistive voltage drop can be achieved using very few layers of thick metal whose thicknesses increase rapidly in ascending layers. Also, using the upper layers for power distribution and lower layers for signal routing results in the most wire length available for signal routing.     

Emitter excess resistance in GaAlAs/GaAs heterojunction bipolar transistors

Numerous studies have shown the influence of parasitic elements, particularly emitter access resistance and inductance, on HBTs DC and dynamic performances. Instead the achievement of low specific contact resistances, the apparent emitter resistance presents high values. To explain this discrepancy the longitudinal distribution of the emitter current has been investigated by using a distributed DC-model, taking into account the metal layers resistance of the different contacts. Thus it is shown that only the emitter contact parameters act on the non equipotentiality along the structure.     

A new concept for making fine line substrate for active component in polymer

Miniaturization in electronics means finer lines and smaller vias in substrate technology. Very fine lines on the substrate are difficult to produce by conventional PWB manufacturing means. Thick copper layers are difficult to etch and the accuracy of conventional dry film photoresist is not necessarily sufficient. On the other hand, the environmental issues force us to reduce pollution.In this paper a new concept (FSBC)^® for making thin, buried active component in polymer, non-reinforced PWB, using electroformatting, dry process (sputtering), electrical lithography and growing processes, via holes and build-up method, is described.To find reliability, tests of peel strength, roughness and some pre-treatments, which act on the adhesion of metal to the dielectric layer between circuits, have been made. Similarly in the tests, the capability of the electrodeposited photosensitive lithography has been compared with the results of the dry and the spin coated liquid films.