超薄栅介质MOSFET直接隧穿电流自洽解模型

采用自洽解方法求解一维薛定谔方程和二维泊松方程,得到电子的量子化能级和相应的浓度分布,利用MWKB方法计算电子隧穿几率,从而得到不同栅偏置下超薄栅介质MOSFET的直接隧穿电流模型。一维模拟结果与实验数据十分吻合,表明了模型的准确性和实用性。二维模拟结果表明,低栅压下,沟道边缘隧穿电流远大于沟道中心隧穿电流,沟道各处的隧穿电流均大于一维模拟结果;高栅压下,隧穿电流在沟道的分布趋于一致,且逼近一维模拟结果。     

一个适用于短沟HALO结构MOS器件的直接隧穿栅电流模型

对沟道长度从10μm到0.13μm,栅氧化层厚度为2.5nm的HALO结构nMOS器件的直接隧穿栅电流进行了研究,得到了一个适用于短沟道HALO结构MOS器件的直接隧穿栅电流模型.随着沟道尺寸的缩短,源/漏扩展区占据沟道的比例越来越大,源漏扩展区的影响不再可以忽略不计.文中考虑了源/漏扩展区对直接隧穿栅电流的影响,给出了适用于不同HALO掺杂剂量的超薄栅(2～4nm)短沟(0.13～0.25μm)nMOS器件的半经验直接隧穿栅电流模拟表达式.     

一个适用于短沟HALO结构MOS器件的直接隧穿栅电流模型

对沟道长度从10μm到0.13μm,栅氧化层厚度为2.5nm的HALO结构nMOS器件的直接隧穿栅电流进行了研究,得到了一个适用于短沟道HALO结构MOS器件的直接隧穿栅电流模型.随着沟道尺寸的缩短,源/漏扩展区占据沟道的比例越来越大,源漏扩展区的影响不再可以忽略不计.文中考虑了源/漏扩展区对直接隧穿栅电流的影响,给出了适用于不同HALO掺杂剂量的超薄栅(2～4nm)短沟(0.13～0.25μm)nMOS器件的半经验直接隧穿栅电流模拟表达式.     

栅隧穿电流分量研究

MOS器件尺寸缩减,导致栅氧化层厚度急剧减小,引起栅隧穿电流的迅速增大,对MOS器件特性产生了很大影响。该文基于此,重点分析和研究了栅隧穿电流分量及其特性,并针对四端MOS器件给出了相应的栅隧穿电流分量测试原理及构思。     

超薄栅MOS结构恒压应力下的直接隧穿弛豫谱

随着器件尺寸的迅速减小 ,直接隧穿电流将代替 FN电流而成为影响器件可靠性的主要因素 .根据比例差值算符理论和弛豫谱技术 ,针对直接隧穿应力下超薄栅 MOS结构提出了一种新的弛豫谱——恒压应力下的直接隧穿弛豫谱 (DTRS) .该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点 ,能够分离和表征超薄栅 MOS结构不同氧化层陷阱 ,提取氧化层陷阱的产生 /俘获截面、陷阱密度等陷阱参数 .直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅 MOS结构中陷阱的产生和复合 ,为超薄栅 MOS结构的可靠性研究提供了一强有力工具 .     

超薄栅MOS结构恒压应力下的直接隧穿弛豫谱

随着器件尺寸的迅速减小,直接隧穿电流将代替FN电流而成为影响器件可靠性的主要因素.根据比例差值算符理论和弛豫谱技术,针对直接隧穿应力下超薄栅MOS结构提出了一种新的弛豫谱--恒压应力下的直接隧穿弛豫谱(DTRS).该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点,能够分离和表征超薄栅MOS结构不同氧化层陷阱,提取氧化层陷阱的产生/俘获截面、陷阱密度等陷阱参数.直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅MOS结构中陷阱的产生和复合,为超薄栅MOS结构的可靠性研究提供了一强有力工具.     

MOSFET栅氧泄漏隧穿电流的分析模型:量子力学研究(英文)

研发了一种通过MOSFET的超薄栅氧化物分析直接隧穿电流密度的模型。采用Wentzel-Kramers-Brilliouin(WKB)近似计算了隧穿概率,利用清晰的表面势方程改进模型的准确性。在研究模型中考虑了Si衬底中反型层的量子化和多晶硅栅耗尽,还研究了多晶硅掺杂对栅氧化层隧穿电流的影响。仿真结果表明,栅氧化层隧穿电流随多晶硅栅掺杂浓度的增加而增加。该结论与已报道的结果相吻合,从而证明了该模型的正确性。     

粗糙界面对超薄栅MOS结构的直接隧穿电流的影响

研究了粗糙界面对电子隧穿超薄栅金属-氧化物-半导体场效应晶体管的氧化层的影响.对于栅厚为3nm的超薄栅MOS结构的界面用高斯粗糙面进行模拟来获取界面粗糙度对直接隧穿电流的影响,数值模拟的结果表明:界面粗糙度对电子的直接隧穿有较大的影响,且直接隧穿电流随界面的粗糙度增加而增大,界面粗糙度对电子的直接隧穿的影响随着外加电压的增加而减小.     

粗糙界面对超薄栅MOS结构的直接隧穿电流的影响

研究了粗糙界面对电子隧穿超薄栅金属 -氧化物 -半导体场效应晶体管的氧化层的影响 .对于栅厚为 3nm的超薄栅 MOS结构的界面用高斯粗糙面进行模拟来获取界面粗糙度对直接隧穿电流的影响 ,数值模拟的结果表明 :界面粗糙度对电子的直接隧穿有较大的影响 ,且直接隧穿电流随界面的粗糙度增加而增大 ,界面粗糙度对电子的直接隧穿的影响随着外加电压的增加而减小 .     

不同厚度超薄栅氧化物MOSFET的应力诱导漏电流

研究了不同厚度的超薄栅1.9nm到3.0 nm器件在恒压应力下的栅电流变化.实验结果显示应力诱导漏电流包括两个部分,一部分是由界面陷阱辅助隧穿引起的,另一部分是氧化物陷阱辅助隧穿引起的.     

利用FN振荡电流测量薄栅MOS结构栅氧化层中隧穿电子的有效质量

给出了一种利用 FN振荡电流的极值 ,测量电子在薄栅 MOS结构的栅氧化层中的平均有效质量方法 .利用波的干涉方法来处理电子隧穿势垒的过程 ,方便地获得了出现极值时外加电压和电子的有效质量之间的分析表达式 .用干涉方法计算所得到的隧穿电子在不同的 MOS结构的二氧化硅介质层中的有效质量表明 :它一般在自由电子质量的 0 .5 2— 0 .84倍的范围 .实验结果表明 :电子有效质量的值不随外加电压的变化而变化 ,并且对于相同的MOS结构 ,电子可能具有相同的有效质量     

Scaling effects on gate leakage current

Scaling effects on direct tunneling gate leakage current are analyzed by utilizing new models implemented to perform self-consistent calculation between the direct tunneling, the band-gap narrowing (BGN) and the incomplete impurity ionization. This calculation is indispensable for reproducing the measured gate current-gate voltage characteristics in the device simulation. As a result, it is concluded that the scaling of the gate width cannot suppress the gate leak, even if the specification of the threshold voltage is relaxed in order to shrink the gate width. It is also found that the scaling of the gate length cannot suppress the gate leak unless the vertical field is strong.     

Characteristics of p-channel Si nano-crystal memory

In this work, the feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. By comparing the programming characteristics of devices with nano-crystals and devices without nano-crystals, the role of dots as storage node is presented. The programming and erasing mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. In case of erasing, the electron tunneling occurs from either the conduction band or the valence band. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time     

New observation and the modeling of gate and drain currents inoff-state P-MOSFET's

The work reports new observations concerning the gate and drain currents measured at off-state conditions in buried-type p-channel LDD MOSFET devices. Detailed investigation of the observed phenomena reveals that 1) the drain current can be separated into two distinct components: band-to-band tunneling in the gate-to-drain overlap region and collection of holes generated via impact ionization by electrons inside the oxide; and 2) the gate current can be separated into two distinct components: the hot electron injection into the oxide and the Fowler-Nordheim electron tunneling through the oxide, At low negative drain voltage, the dominant component of the drain current is the hole generation inside the oxide. At high negative drain voltage, the drain current is essentially due to band-to-band tunneling, and it is correlated with the hot-electron injection-induced gate current     

Tunneling into interface states as reliability monitor for ultrathin oxides

This paper reports experimental data and simulations of low-voltage tunneling in ultrathin oxide MOS devices. When the substrate is very heavily doped, a thermionic barrier is present that opposes the direct tunneling of gate electrons when the applied gate voltage is between 0 V and the flatband voltage. In such conditions, we show that the measured gate current cannot be explained by direct tunneling, but features an additional, dominant component. The temperature dependence of this extra component indicates that it is due to gate electrons tunneling into the anode interface states. By comparing measurements and simulations, it is possible to exploit this extra current to estimate the interface state density within the silicon band gap. In addition, it is shown that this tunneling current component is very sensitive to electrical stress and allows a clear detection of oxide wear out even for stress at very low field. Therefore, it can be adopted as monitor of oxide degradation in ultrathin oxides where the traditional stress induced leakage current due to bulk-oxide traps is not detectable.     

Effects of high field stresses on threshold voltage of CMOS transistors

In this paper, the threshold voltage instabilities of CMOS transistors under gate bias stress at high gate oxide electric fields have been investigated. It is shown that in presence of the negative gate bias stress threshold voltage of n-channel MOSTs decreases, while threshold voltage of p-channel MOSTs increases. These results are explained by positive fixed oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps. On the other hand, it is shown that in the presence of the positive gate bias stress threshold voltage of n-channel MOSTs decreases at the beginning as well, but after a certain time period starts to increase, while threshold voltage of p-channel MOSTs continuously increases. The initial threshold voltage behaviour is explained by positive fixed oxide charge increase as well; however, in this case it is caused by the electron tunneling from oxide electron traps into oxide conduction band. The later threshold voltage increase of n-channel MOSTs is explained by surface state charge increase due to tunnel current flowing through the oxide.     

New mechanism of gate current in heterostructure insulated gate field-effect transistors

We demonstrate that the mechanism responsible for the gate current in heterostructure insulated gate field-effect transistors (HIGFET's) changes drastically at the gate voltage equal to the threshold voltage. At the gate voltages below the threshold voltage the gate current is determined by the thermionic emission over the Schottky barrier at high temperatures and by the thermionic field emission at low temperatures. Above the threshold the gate current is determined by the new mechanism which is the thermionic emission over the conduction band discontinuity at high temperatures and by tunneling through the AlGaAs layer at low temperatures. We present the model describing the gate current in the entire range of the gate voltages and device temperatures.     

Reliability of ultrathin silicon dioxide under combined substratehot-electron and constant voltage tunneling stress

An experimental investigation of breakdown and defect generation under combined substrate hot-electron and tunneling electrical stress of silicon oxide ranging in thickness from 2.0 nm to 3.5 nm is reported. Using independent control of the gate current for a given substrate and gate bias, the time-to-breakdown of ultrathin silicon dioxide under substrate hot-electron stress is observed to be inversely proportional to the gate current density. The thickness dependence (2.0 nm to 3.5 nm) of substrate hot-electron reliability is reported and shown to be similar to constant voltage tunneling stress. The build-up of defects measured using stress-induced-leakage-current and charge-pumping for both tunneling and substrate hot-electron stress is reported. Based on these and previous results, a model is proposed to explain the time-to-breakdown behavior of ultrathin oxide under simultaneous tunneling and substrate hot-electron stress. The results and model provide a coherent understanding for describing the reliability of ultrathin SiO₂ under combined substrate hot-electron injection and constant voltage tunneling stress     

Polarity dependent gate tunneling currents in dual-gate CMOSFETs

Polarity dependence of the gate tunneling current in dual-gate CMOSFETs is studied over a gate oxide range of 2-6 nm. It is shown that, when measured in accumulation, the I_g versus V_g characteristics for the p⁺/pMOSFET are essentially identical to those for the n⁺/nMOSFET; however, when measured in inversion, the p⁺/pMOSFET exhibits much lower gate current for the same |V_g|. This polarity dependence is explained by the difference in the supply of the tunneling electrons. The carrier transport processes in p⁺/pMOSFET biased in inversion are discussed in detail. Three tunneling processes are considered: (1) valence band hole tunneling from the Si substrate; (2) valence band electron tunneling from the p⁺-polysilicon gate; and (3) conduction band electron tunneling from the p⁺-polysilicon gate. The results indicate that all three contribute to the gate tunneling current in an inverted p⁺/pMOSFET, with one of them dominating in a certain voltage range     

不同厚度超薄栅氧化物MOSFET的应力诱导漏电流

研究了不同厚度的超薄栅1.9nm到3.0nm器件在恒压应力下的栅电流变化.实验结果显示应力诱导漏电流包括两个部分,一部分是由界面陷阱辅助隧穿引起的,另一部分是氧化物陷阱辅助隧穿引起的.