整数5/3小波变换的VLSI结构设计

在JPEG 2000中,无损图像压缩是采用整数5/3小波变换实现的.JPEG 2000也给出了5/3小波基于提升方法的算法.对提升方法的整数5/3小波变换算法进行了研究,针对二维的变换提出一种VLSI结构.该结构由4个模块构成,模块之间并行运行,模块内部采用流水线技术.对多级变换,级间的运算还可交叉,体现了提升方法的优势,较大地提高了硬件效率.其主要优点是消耗资源少且运算速度高,同时也适用于其他整数小波变换.     

一种适合JPEG2000的离散小波变换VLSI统一结构

提出了一种基于提升算法(1ifting)的离散小波变换(DWT)统一结构。它无需额外的边界延拓过程，经配置后可适用于JPEG2000中的无损或有损小波变换。通过将边界延拓过程内嵌于离散小波变换中，可以降低功耗，减少所需内存。为了达到更高的处理速度和硬件利用率，采用了流水线和折叠结构。这种高效紧凑的离散小波变换结构适用于JPEG2000编码器和各种实时图像／视频应用系统．     

低功耗并行的提升式5/3二维离散小波变换的VLSI架构

离散小波变换需要较大的运算量和运算空间,为了提高JPEG2000图像压缩速度,提出一种基于提升算法的二维离散5/3小波变换的VLSI架构,这种结构同时进行行变换和列变换。文章对于VLSI架构的五大模块(行小波变换运算模块、两个列小波变换模块、FIFO寄存组和系统整体控制模块)的硬件实现给出了相应的方案。在Quartus II 7.2的平台下对于设计的该系统的时序仿真测试结果表明,综合分析后系统最小组合逻辑时延为7.142ns,可达到的最高频率为140.02MHz。时序仿真测试中当系统工作频率为100MHz,数据吞吐率达到773.944Mbit/s。     

二维9/7小波变换VLSI设计

为了提高JPEG2000图像压缩速度,提出一种基于提升算法的二维离散9/7小波变换(DWT)Mesh结构的VLSI设计方案,利用这种Mesh结构的VLSI能够实现并行处理一个图像的所有像素点.这种并行处理的Mesh结构可提高小波变换电路速度,以及图像压缩的速度.     

一种高性能9/7离散小波变换滤波器的硬件设计

基于提升格式的离散小波变换比传统的基于卷积的运算量少,易于VLSI实现。本文提出了一种基于提升格式,高效实时实现JPEG2000中9/7双正交离散小波变换滤波器的VLSI结构设计方法。该方法所设计的结构,在保证同样的精度下,减少了运算量,整体运算速度高,硬件花费少,存储需求低,硬件利用率达到100%。本文用Verilog HDL对系统进行硬件描述,并选用Xilinx公司的XCV50e-cs144-8器件在ISE4.1环境下实现了综合。     

JPEG2000小波变换仿真

提出一种基于JPEG2000中推荐的提升结构的5/3小波变换硬件实现方案。该方案在加载数据的同时进行边界扩展,无须对运算电路进行逻辑控制,可以复用加法器,提高了资源利用率。该方案在FPGA上仿真通过。     

JPEG2000算法中基于有界输入有界输出(BIBO)增益控制的小波变换定点实现技术

该文提出一种在JPEG2000算法中兼容5/3小波变换和9/7小波变换高效硬件定点实现技术。所提出的技术使用9/7提升小波变换的有界输入有界输出(Bounded Input Bounded Output, BIBO)增益来确定小波变换中间值的存储位深,使用5/3提升小波变换的BIBO增益来确定9/7提升小波变换中量化参数的选择方式和量化的实现方式,最终使用同一存储空间来存放定点5/3提升小波变换和定点9/7提升小波变换系数。该文提出的技术不仅大大节省了JPEG2000算法中小波实现模块中的硬件存储资源和算法计算量,而且也节省了后续基于上下文的位平面算术编码模块和率失真优化截取模块的存储资源和算法计算量。     

JPEG2000小波变换器的VLSI结构设计

新一代静止图像压缩标准JPEG2000将离散小波变换(DWT)作为其核心变换技术,并推荐采用推举体制(lifting)快速算法来实现.空间组合推举体制算法(SCLA)大大降低了lifting的运算量.当选用9/7小波滤波器时,SCLA的乘法运算量只有lifting的7/12.本文提出了一种实现SCLA算法的VLSI结构,降低了基于lifting实现的运算量, 加快了变换的速度,减小了电路的规模.本文的二维正反小波变换器已经作为单独的IP核应用于我们目前正在开发的JPEG2000图像编解码芯片中.     

HEVC静态图像压缩与JPEG2000性能比较与分析

基于离散小波变换DWT(Discrete Wavelet Transform)的JPEG 2000代表着静态图像的最高水平.HEVC(High Efficiency Video Coding)提出了一个静态图像压缩档次——Main Still Profile,其帧内编码模式采用多种新的算法实现.通过大量实验比较发现,基于HEVC静态图像压缩比JPEG 2000具有更高的压缩效率,将来有望取代JPEG 2000成为新的静态图像压缩标准.     

应用于JPEG2000的5/3提升小波的VLSI结构设计

提出一种基于提升算法（lifting scheme）实现JPEG2000编码系统中的二维离散小波变换（Discrete Wavelet Transform）的并行阵列式的VLSI结构设计方法.该结构由一个行处理器和一个列处理器组成,行、列处理器通过时分复用同时进行滤波,用优化的移位加操作替代乘法操作,采用嵌入式数据延拓算法处理边界延拓.整个结构采用流水线设计方法,减少了运算量,提高了硬件资源利用率,该结构可应用于JPEG2000图像编码芯片中.     

JPEG2000并行阵列式小波滤波器的VLSI结构设计

提出一种基于提升算法实现JPEG2000编码系统中的二维离散小波变换(Discrete Wavelet Transform)的并行阵列式的VLSI结构设计方法.利用该方法所得结构由两个行处理器,一个列处理器以及少量行缓存组成;行列处理器内部是由并行阵列式的处理单元组成;能使行和列滤波器同时进行滤波,用优化的移位加操作替代乘法操作.整个结构采用流水线的设计方法处理,在保证同样的精度下,大大减少了运算量和提高了硬件资源利用率,几乎达到100％,加快了变换速度,也减少了电路的规模.该结构对于N×N大小的图像,处理速度达到O(N²/2)个时钟周期.二维离散小波滤波器结构已经过FPGA验证,并可作为单独的IP核应用于正在开发的JPEG2000图像编解码芯片中.     

An Efficient Pipeline Architecture and Memory Bit-Width Analysis for Discrete Wavelet Transform of the 9/7 Filter for JPEG 2000

In this paper, we propose an efficient pipeline architecture for the DWT 9/7 filter defined in JPEG 2000. The proposed architecture is composed of column and row processors to perform the separable 2-D DWT. Based on the rescheduling DWT algorithm, we derive a new data flow graph to shorten the critical path. The proposed 1-D column processor requires less pipeline registers to achieve about the same critical path compared with other lifting-based architectures. For the row processor, the data dependency of each lifting step is reduced to only two computation nodes and therefore more pipeline registers can be applied to achieve higher processing speed without increasing the internal memory size in the 2-D case. That is, for an N × N image, it only requires 4N internal memory to perform the row-wise transform. For the memory bit-width analysis, we use software simulation to reduce the memory bit-width for various compression ratios. Since a portion of information from least significant bits of DWT coefficients would be discarded after EBCOT-tier2 processing, one can decrease the data width of internal memory to perform various compression ratios of JPEG 2000 coding, especially at the low-bit rates. Our simulation results suggest that it is practically possible to design the energy-aware memory architecture to further reduce the power consumption in the future work.     

基于GPGPU的JPEG2000图像压缩方法

为了进一步加快JPEG2000的压缩速度,对JPEG2000压缩标准进行研究,分析得出JPEG2000核心算法离散小波变换（DWT）部分数据之间的独立性适合并行化处理。NVIDIA最新推出的CUDA（计算统一设备架构）是非常适合大规模数据并行计算的软硬件开发平台。在通用计算图形处理器（general purpose graphic process unit, GPGPU）上使用CUDA技术实现DWT并行化加速,并针对GPGPU存储空间的特点进行优化。得出的实验结果表明,经过CUDA并行优化的方法能够有效地提高DWT的计算速度。     

SPIHT静止图像压缩技术研究

JPEG2000的静止图像压缩算法具有很多优良特性,其核心算法是EBCOT,构造复杂、硬件实现难度大。而基于SPIHT算法的图像压缩效率接近EBCOT,但结构简单、易于硬件实现。通过对SPIHT和JPEG2000算法进行融合,提出了一套压缩比高、可实现由有损到无损、码流渐进传输的静止图像编码方案,并对SPIHT算法与(9,7)小波提升算法的融合方法进行分析研究,所构造系统性能与JPEG2000算法接近,具有较好的应用前景。     

JPEG2000中DWT-EBCOT联合的高效低存储VLSI结构

针对JPEG2000硬件实现中小波变换与编码之间占用大量存储的问题,该文提出一种基于码块的存储方案。通过对码块大小片内存储最大程度的复用以及对其高效简单的调度控制,从面积和功耗两方面减小了硬件实现的开销。在实现中,采用基于行的提升变换结构和比特平面并行的编码方式,提高了效率,确保整个过程的实时处理。实验结果表明:在实时编码要求下,对分辨率为512512的图像分片进行四级9/7或者5/3小波分解,码块大小为3232,采用本文结构所用的存储量与直接使用外部存储器的方法相比可减少80%以上。整个结构已通过FPGA验证,且系统时钟可以工作在100MHz。     

Image coding using lapped biorthogonal transform

The wireless sensor network utilizes image compression algorithms like JPEG, JPEG2000, and SPIHT for image transmission with high coding efficiency. During compression, discrete cosine transform (DCT)–based JPEG has blocking artifacts at low bit-rates. But this effect is reduced by discrete wavelet transform (DWT)–based JPEG2000 and SPIHT algorithm but it possess high computational complexity. This paper proposes an efficient lapped biorthogonal transform (LBT)–based low-complexity zerotree codec (LZC), an entropy coder for image coding algorithm to achieve high compression. The LBT-LZC algorithm yields high compression, better visual quality with low computational complexity. The performance of the proposed method is compared with other popular coding schemes based on LBT, DCT and wavelet transforms. The simulation results reveal that the proposed algorithm reduces the blocking artifacts and achieves high compression. Besides, it is analyzed for noise resilience.     

A comparison of hardware implementations of the biorthogonal 9/7 DWT: convolution versus lifting

The filter bank approach for computing the discrete wavelet transform (DWT), which we call the convolution method, can employ either a nonpolyphase or polyphase structure. This work compares filter banks with an alternative polyphase structure for calculating the DWT-the lifting method. We look at the traditional lifting structure and a recently proposed "flipping" structure for implementing lifting. All filter bank structures are implemented on an Altera field-programmable gate array. The quantization of the coefficients (for implementation in fixed-point hardware) plays a crucial role in the performance of all structures, affecting both image compression quality and hardware metrics. We design several quantization methods and compare the best design for each approach: the nonpolyphase filter bank, the polyphase filter bank, the lifting and flipping structures. The results indicate that for the same image compression performance, the flipping structure gives the smallest and fastest, low-power hardware.     

Listless block-tree set partitioning algorithm for very low bit rate embedded image compression

This paper presents a listless implementation of wavelet based block tree coding (WBTC) algorithm of varying root block sizes. WBTC algorithm improves the image compression performance of set partitioning in hierarchical trees (SPIHT) at lower rates by efficiently encoding both inter and intra scale correlation using block trees. Though WBTC lowers the memory requirement by using block trees compared to SPIHT, it makes use of three ordered auxiliary lists. This feature makes WBTC undesirable for hardware implementation; as it needs a lot of memory management when the list nodes grow exponentially on each pass. The proposed listless implementation of WBTC algorithm uses special markers instead of lists. This reduces dynamic memory requirement by 88% with respect to WBTC and 89% with respect to SPIHT. The proposed algorithm is combined with discrete cosine transform (DCT) and discrete wavelet transform (DWT) to show its superiority over DCT and DWT based embedded coders, including JPEG 2000 at lower rates. The compression performance on most of the standard test images is nearly same as WBTC, and outperforms SPIHT by a wide margin particularly at lower bit rates.