Planar normally-off GaAs JFET for high speed logic circuits

Normally-off JFETs with 1.3 ?m-long gates were fabricated by selective double ion implantation for the n and n+ regions and selective Zn diffusion for the p-gate area. A JFET with a 10 ?m-wide gate had a transconductance of 2 mS in average and a high value of 3 mS. A 15 stage ring oscillator made of resistively loaded DCFLs showed the minimum delay time of 45 ps, the shortest value obtained based on optical lithography. The minimum power-delay product was 3.8 fJ with a delay time of 83 ps.     

Femtojoule logic circuit using normally-off GaAs m.e.s.f.e.t.s

Experimental results are reported on the speed/power performance of normally-off-type GaAs-m.e.s.f.e.t. logic circuits, using an integrated 15-stage ring oscillator as a test circuit. A power consumption as low as 1-5 ?W, corresponding to a power-delay product of 1.6 fJ, was obtained. Conversely, a propagation delay time of 650 ps was measured for a power consumption of 20 ?W per gate.     

Planar GaAs MOSFET integrated logic

Selective and multiple ion implantations directly into a semi-insulating GaAs substrate were utilized to fabricate planar integrated circuits with deep-depletion plasma-grown native oxide gate GaAs MOSFET's. 1.2-µm gate 27-stage enhancement/depletion (E/D) type ring oscillators, with the circuit optimized to reduce parasitic capacitance, were fabricated (using conventional photolithography) to assess the speed-power performance in digital applications. A minimum propagation delay of 72 ps with a power-delay product of 139 fJ was obtained, making these devices the fastest among current GaAs and Si logic fabricated by conventional photolithography. A minimum power-delay product of 36 fJ with a propagation delay of 157 ps was obtained. The power-delay product is comparable with that of 1.2-µm gate GaAs E-MESFET logic, and the speed is more than twice as great. This paper includes a comparison of the theoretical cut off frequency of MESFET and MOSFET logic devices operating in depletion mode. Results indicate that MOSFET logic has superior potential for high-speed operation.     

Direct-coupled logic operation of GaAs column gate FET

A ring oscillator operation is demonstrated employing normally-off 2 µm diameter column gate FET with 145 ps/gate delay time and with 64 fJ power-delay product. Delay time is discussed in terms of CR time constant comparison between MES and column structure. The column gate FET can realize much smaller "on" resistance comparing with MESFET.     

Performance prediction for submicron GaAs SDFL logic

We report the results of the computer simulation of GaAs SDFL (Schottky diode FET logic) ring oscillators which takes into account transient effects leading to higher electron velocity in short devices and the fringing capacitances. The results indicate that the delay time decreases from 53.6 ps for 1 µm devices to 28.1 ps for 0.5 µm gate devices, and to 18.6 ps for 0.25 µm devices, with power-delay products of 229, 70, and 27.1 fJ, respectively. When the transient effects are not taken into account, the power-delay product remains nearly the same but the delay time increases with the largest increase to 27 ps for .25 µm devices.     

Dependence of normally-off GaAs JFET performance on device structure

The relation between the performance of normally-off JFET's and the Si ion-implantation conditions used to form the channel layer was studied. Static and switching characteristics were investigated for JFET's with three kinds of channel layers; Si implanted at 130 keV to doses of 2,4, and 6 × 10¹²ions/cm². While higher doses gave better static characteristics [Ids, gm, and Ron], higher capacitance degraded the switching characteristics. The optimum parameters were determined for the high-speed switching JFET. With 2-µm gate length, the highest switching speed was 80 ps and the lowest power-delay product was 0.9 fJ. An improved structure satisfying a high-conductance and low-capacitance requirement was successfully fabricated and showed excellent performance for high-speed and low-power logic circuits; the minimum propagation delay was 45 ps and the minimum power-delay product was 3.8 fJ with a delay time of 83 ps.     

11 ps ring oscillators with submicrometre selectively doped heterostructure transistors

Selectively doped AlGaAs/GaAs heterostructure transistor (SDHT) ring oscillators with submicrometre gates have been fabricated using electron beam lithography. Minimum propagation delay of 11.0 ps/gate at 77 K was measured on a 0.4 ?m gate-length ring oscillator with a power-delay product of 15 fJ at 1.1 V bias. The processing of these structures is described, as well as the testing of the submicrometre transistors and circuits at 300 K and 77 K.     

AlGaAs/GaAs MESFET IC with Ni buried gate technology

Ni buried gate technology for threshold voltage control using a Ni-GaAs reaction by a heat treatment is developed and successfully applied to AlGaAs/GaAs heterostructure MESFET IC's. Switching delay time of 36.7 ps with the power-delay product of 10 fJ (1-V supply voltage) was obtained at 83 K for a ring oscillator with 1.5-µm gate FET's. This technology, together with the saturated resistor loads, promises to simplify the process for AlGaAs/GaAs MESFET LSI's by not requiring active-layer etching.     

New Technology Towards GaAs LSI/VLSI for Computer Applications

For future large-scale computer applications, new device technologies towards GaAs LSI/VLSI have been developed self-aligned fully implanted planar GaAs MESFET technology and high electron mobility transistor (HFMT) technology by molecular beam epitaxy (MBE). The self-aligned GaAs MESFET logic with 1.5-µm gate length exhibits a minimum switching time of 50 ps and the lowest power-delay product of 14.5 fJ at room temperature. The enhancement/depletion (E/D) type direct coupled HEMT logic has achieved a switching time of 17.1 ps with 1.7-µm gate length at liquid nitrogen temperature and more recently a switching time of 12.8 ps with 1.1-µm gate HEMT logic, which exceeds the top speed of Josephson Junction logic and shows the highest speed of any device logic ever reported. Optimized system performances are also projected to system delay of 200 ps at 10-kilogate integration with GaAs MESFET VLSI, and 100 ps at 100-kilogate with HEMT VLSI. These values of system delay correspond to the computer performance of over 100 million instructions per second (MIPS).     

An optically defined 1.3-µm NMOS ring oscillator

n-channel enhancement/depletion (E/D) gate MOS ring-oscillators (RO) based on 1.3- and 2-µm layout design rules have been fabricated using 10:1 reduction projection aligner. A delay/stage of 80 ps and a power-delay product of 3.6 fJ have been obtained for a 401-stage RO consisting of 1.3-µm feature-size devices.     

New technology towards GaAs LSI/VLSI for computer applications

For future large-scale computer applications, new device technologies towards GaAs LSI/VLSI have been developed: self-aligned fully implanted planar GaAs MESFET technology and high electron mobility transistor (HEMT) technology by molecular beam epitaxy (MBE). The self-aligned GaAs MESFET logic with 1.5-µm gate length exhibits a minimum switching time of 50 ps and the lowest power-delay product of 14.5 fJ at room temperature. The enhancement/depletion (E/D) type direct coupled HEMT logic has achieved a switching time of 17.1 ps with 1.7-µm gate length at liquid nitrogen temperature and more recently a switching time of 12.8 ps with 1.1-µm gate HEMT logic, which exceeds the top speed of Josephson Junction logic and shows the highest speed of any device logic ever reported. Optimized system performances are also projected to system delay of 200 ps at 10-kilogate integration with GaAs MESFET VLSI, and 100 ps at 100-kilogate with HEMT VLSI. These values of system delay correspond to the computer performance of over 100 million instructions per second (MIPS).     

High-Speed Enhancement-Mode GaAs MESFET Logic

High-speed enhancement-mode GaAs MESFET Iogic circuits have been fabricated by electron beam lithography. A 15-stage ring oscillator composed of 0.8-mu m gatelength and 40-mu m gatewidth inverters has given a minimum propagation delay time of 77 ps at a power dissipation of 977 mu W. A minimum power-delay product of 1.6 fJ has been obtained with a 20-mu m gatewidth circuit at a propagation delay time of 200 ps. Liquid nitrogen temperature operation has also been performed, and a speed almost twice higher than that at room temperature has been obtained. The minimum propagation delay time was 51 ps, and the associated power dissipation was 1.9 mW.     

Highly doped InGaP/InGaAs/GaAs pseudomorphic HEMT's with 0.35 μmgates

We fabricated 0.35-μm gate-length pseudomorphic HEMT DCFL circuits using a highly doped thin InGaP layer as the electron supply layer. The InGaP/InGaAs/GaAs pseudomorphic HEMT grown by MOVPE is suitable for short gate-length devices with a low supply voltage since it does not show short channel effects even for gate length down to 0.35 μm. We obtained a K value of 555 mS/Vmm and a transconductance g_m of 380 mS/mm for an InGaP layer 18.5 nm thick. Fabricated 51-stage ring oscillators show the basic propagation delay of 11 ps and the power-delay product of 7.3 fJ at supply voltage of V_DD of 1 V, and 13.8 ps and 3.2 fJ at V_DD of 0.6 V for gates 10 μm wide     

A 1-μm polysilicon self-aligning bipolar process for low-powerhigh-speed integrated circuits

A double-poly-Si self-aligning bipolar process employing 1-μm lithography is developed for very-high-speed circuit applications. Epilayer doping and thickness are optimized for breakdown voltages and good speed-power performance. Shallow base-emitter profiles are obtained by combining low-energy boron implantation and rapid thermal annealing (RTA) for the emitter drive-in. A transit frequency f_T =14 GHz at V_BC=-1 V and a current-mode-logic (CML) gate delay of 43 ps at 30 fJ are achieved. For an emitter size of 1.0×2.0 μm² a minimum power-delay product of 15 fJ is calculated. Circuit performance capability is demonstrated by a static frequency divider operating up to 15 GHz     

A scaled 0.25-μm bipolar technology using full e-beamlithography

The full leverage offered by electron-beam lithography has been exploited in a scaled 0.25-μm double polysilicon bipolar technology. Devices and circuits were fabricated using e-beam lithography for all mask levels with level-to-level overlays tighter than 0.06 μm. Ion implantation was used to form a sub-100-nm intrinsic base profile, and a novel in-situ doped polysilicon emitter process was used to minimize narrow emitter effects. Transistors with 0.25-μm emitter width have current gains above 80 and cutoff frequencies as high as 40 GHz. A record ECL gate delay of 20.8 ps at 4.82 mW has been measured together with a minimum power-delay product of 47 fJ (42.1 ps at 1.12 mW). These results demonstrate the feasibility and resultant performance leverage of aggressive scaling of conventional bipolar technologies     

Operation of bulk CMOS devices at very low temperatures

Low-temperature (77K, 4.2K) operation is proposed for bulk CMOS devices to be used in superfast VLSI applications. Symmetrical variation of the parameters of both n-channel and p-channel MOSFETs with respect to the temperature and latch-up immunity makes CMOS a very promising device technology at low temperatures. To demonstrate the performance advantage of circuit operation at low temperatures, inverter chains and 16-kb static random-access memories (RAMs) with 2-/spl mu/m gate length were measured. Average propagation delay for an inverter chain has been reduced to 175 ps (77K) and 104 ps (4.2K) from 296 ps at 300K without sacrificing power dissipation. The power-delay product is less 1 fJ, which is the smallest for silicon devices reported to date. The chip select-access time of the RAM has been reduced to 14.3 ns (77K) from 24 ns (300K).     

A high-speed complementary silicon bipolar technology with 12-fJpower-delay product

A complementary silicon bipolar technology offering a substantial improvement in power-delay performance over conventional n-p-n-only bipolar technology is demonstrated. High-speed n-p-n and p-n-p double-polysilicon, self-aligned transistors were fabricated in a 20-mask-count integrated process using an experimental test site designed specifically for complementary bipolar applications. N-p-n and p-n-p transistors with 0.50-μm emitter widths have cutoff frequencies of 50 GHz and 13 GHz, respectively. Two novel complementary bipolar circuits-AC-coupled complementary push-pull ECL, and NTL with complementary emitter-follower-display a significant advantage in power dissipation as well as gate delay when compared to conventional n-p-n-only ECL circuits. Record power-delay products of 34 fJ (23.2 ps at 1.48 mW) and 12 fJ (19.0 ps at 0.65 mW) were achieved for these unloaded complementary circuits, respectively. These results demonstrate the feasibility and resultant performance leverage of high-speed complementary bipolar technologies     

High-performance bipolar technology for improved ECL power delay

A new shallow trench process for isolation of bipolar devices is shown to allow butting of the emitter-base junction to the field oxide edge, thereby greatly reducing the overall device size and parasitic capacitances. Emitter-coupled logic (ECL) ring-oscillator measurements demonstrate a significant performance leverage, where a delay of 75 ps is obtained at a power of 1.5 mW per gate (power-delay product of 112 fJ ), an improvement of 17% from the nonbutted case. More conventional nonbutted devices have been fabricated with dopant profiles tailored to reduce intrinsic and extrinsic capacitances. These high-performance designs achieve ECL gate delays as small as 26 ps at 5.3 mW, comparable to the fastest ECL delays reported to date     

High-speed GaAs multipliers fabricated with a high-yield 0.4-μmprocess

A 0.4-μm GaAs IC fabrication process which demonstrates excellent yields for direct-coupled FET logic circuits of up to 5000 gates for high-speed LSI digital applications is discussed. The refractory self-aligned gate process uses 1-μm stepper lithography. An n⁺/n'/buried-p structure results in superior threshold voltage uniformity for a 0.4-μm gate length, with σV _T as low as 8 mV over 3-in wafers. Simple parallel array multipliers were used for process validation. Die-sort yields for a 16-b×16-b multiplier are typically better than 55%, and as high as 88%. A 5000-gate 20-b×20-b multiplier shows yield as high as 61%, and a Poisson yield model predicts a die-sort yield of 30% for a 10000-gate circuit. Multiplication times of 3.6 ns for the 16-b×16-b and 4.5 ns for the 20-b×20-b multiplier have been measured. The corresponding loaded gate delay and power-delay product are 46 ps/gate and 40 fJ, respectively, at room temperature     

Inverted transistor gate with FET load

The letter outlines preliminary results on a new logic gate for silicon bipolar VLSI. Gate delays below 4 ns have been achieved at 2 ?W dissipation, demonstrating a power-delay product of only 8 fJ. These results are achieved on a 3 ?m minimum feature size oxide isolated process.