Parallel Adder Design with Reduced Circuit Complexity Using Resonant Tunneling Transistors and Threshold Logic

Quantum-effect devices utilizing resonant tunneling are promising candidates for future nano-scale integration. Originating from the technological progress of semiconductor technology, circuit architectures with reduced complexity are investigated by exploiting the negative-differential resistance of resonant tunneling devices. In this paper a resonant tunneling device threshold logic family based on the Monostable-Bistable Transition Logic Element (MOBILE) is proposed and applied to different parallel adder designs, such as ripple carry and binary carry lookahead adders. The basic device is a resonant tunneling transistor (RTT) composed of a resonant tunneling diode monolithically integrated on the drain contact layer of a heterostructure field effect transistor. On the circuit level the key components are a programmable NAND/NOR logic gate, threshold logic gates, and parallel counters. The special properties of MOBILE logic gates are considered by a bit-level pipelined circuit style. Experimental results are presented for the NAND/NOR logic gate.     

Functions and applications of monostable-bistable transition logicelements (MOBILE's) having multiple-input terminals

The MOBILE is a logic gate exploiting the monostable-bistable transition of a circuit that consists of two resonant tunneling transistors connected in series. It has several advantages including multiple inputs and multiple functions. This paper describes the output characteristics of multiple-input MOBILE's and discusses their applications. For a two-input MOBILE, it is demonstrated that both NAND and NOR operations are possible with the appropriate control voltage. This implies the possibility of a variable function logic gate. Furthermore, the threshold logic operations for a weighted sum of input signals are demonstrated for a three-input MOBILE with a weight ratio of 4:2:1. The applications of MOBILE's in parallel processing architectures such as cellular automata and cellular neural networks are discussed based on the above results. Circuit simulations using a simple model of resonant tunneling transistors successfully reproduce the basic characteristics of MOBILE's, and demonstrate the usefulness of MOBILE's in such applications     

Monolithic integration of resonant tunneling diodes and FET's formonostable-bistable transition logic elements (MOBILE's)

A MOBILE (monostable-bistable transition logic element), employing two n-type negative differential resistance devices connected in series, is a functional logic gate with the advantages of multiple inputs and multiple functions. In this paper, a novel approach to achieve MOBILE operation is demonstrated using monolithic integration of resonant tunneling diodes (RTD) and FETs. In our new integration structure, an RTD and FET are connected in parallel. This structure offers several advantages including separate optimization of RTD's and FET's, and flexible circuit design abilities. For a single-input MOBILE gate, inverter operation at room temperature is demonstrated as the evidence of monostable-to-bistable transition     

RTD/HPT光控单-双稳转换逻辑单元

以光接收器件代替RTD MOBILE(RTD单-双稳转换逻辑单元)电路中的HEMT或HBT,可构成光控MOBILE电路。在比较了四种光控MOBILE结构的基础上,选择RTD/HPT光控结构,重点分析讨论了RTD/HPT光控MOBILE的工作原理,当光控MOBILE的输入光功率超过一个临界值时,MOBILE的输出电压便会从高电平跳变到低电平;由HPT光增益理论分析了提高HPT性能的措施以及HPT设计中应该注意的问题;介绍了以Si光三极管代替HPT,通过模拟实验,验证了RTD/HPT光控MOBILE的逻辑功能。     

共振隧穿器件应用电路概述——共振隧穿器件讲座(2)

在“共振隧穿器件概述”的基础上,对共振隧穿器件应用电路作了全面概括的介绍。首先对共振隧穿器件应用电路的特点、分类和发展趋势作了简述;进一步对由RTDH/EMT构成的单-双稳转换逻辑单元(MOBILE)和以它为基础构成的RTD应用电路,包括柔性逻辑、静态随机存储(SRAM)、神经元、静态分频器等电路的结构、工作原理和逻辑功能等进行了介绍。关于RTD/HEMT构成的更为复杂的电路,如多值逻辑、AD转换器以及RTD光电集成电路等将在本讲座最后部分进行讲解。     

A vertical resonant tunneling transistor for application in digitallogic circuits

A vertical resonant tunneling transistor (VRTT) has been developed, its properties and its application in digital logic circuits based on the monostable-bistable transition logic element (MOBILE) principle are described. The device consists of a small mesa resonant tunneling diode (RTD) in the GaAs/AlAs material system surrounded by a Schottky gate. We obtain low peak voltages using InGaAs in the quantum well and the devices show an excellent peak current control by means of an applied gate voltage. A self latching inverter circuit has been fabricated using two VRTTs and the switching functionality was demonstrated at low frequencies     

Digital integrated circuit using integrated InAlAs/InGaAs/InP HEMTsand InAs/AlSb/GaSb RITDs

The demonstration of the first integrated circuit using monolithically integrated InAs/AlSb/GaSb resonant interband tunnelling diodes (RITDs) and InAlAs/InGaAs/InP high electron mobility transistors (HEMTs) is reported. A D-flip-flop (D-FF) was implemented using the monostable/bistable logic element (MOBILE) circuit architecture, with a measured effective voltage gain in excess of 380. Power dissipation of less than 2.8 mW/gate was measured     

Logic circuit design using monostable-bistable transition logic element based on standard BiCMOS process

We present a monostable-bistable transition logic element (MOBILE) based on the negative-differential-resistance (NDR) circuit. In particular, this circuit can be completely implemented using the standard BiCMOS process. A traditional MOBILE using two resonant tunneling diodes (RTD) connected in series is a functional logic circuit. The fabrication of RTD is utilized in the complicated molecular-beam-epitaxy (MBE) system. However, we present a MOBILE circuit that is completely made of standard Si-based metal-oxide-semiconductor field effect transistors and SiGe-based heterojunction bipolar transistors. By suitably determining the control voltages and input conditions, we can obtain the operation of the inverter, AND and OR logic gates. We also demonstrate the latch characteristic of this MOBILE circuit. This logic circuit is fabricated using the standard 0.35 μm BiCMOS process without the need for the MBE system.     

一种基于RTD和HEMT的单片集成逻辑电路

介绍了一种基于共振隧穿二极管(RTD)和高电子迁移率晶体管(HEMT)的单片集成电路.采用分子束外延技术在GaAs底层上重叠生长了RTD和HEMT结构.RTD室温下的峰谷电流比为5.2∶1,峰值电流密度为22.5kA/cm2.HEMT采用1μm栅长,阈值电压为-1V.设计电路称为单稳态-双稳态转换逻辑单元(MOBILE).实验结果显示了该电路逻辑运行成功,运行频率可达2GHz以上.     

Resonant tunnelling delta sigma modulator suitable for high-speed operation

A resonant tunnelling logic gate, monostable-bistable transition logic element (MOBILE), was used to test high frequency operation of the /spl Delta//spl Sigma/ modulator based on a frequency modulated intermediate signal. This /spl Delta//spl Sigma/ modulator has no feedback loop and is promising for high-speed operation. Good noise shaping characteristics over four decades were measured. This ideal noise shaping demonstrated that the MOBILE can work as an ideal quantiser.     

Design of monostable–bistable transition logic element using the BiCMOS-based negative differential resistance circuit

The monostable–bistable transition logic element (MOBILE) is a promising application for negative differential resistance (NDR) circuit. Previously reported MOBILE is constructed by resonant tunneling diode (RTD) that is implemented by the molecular beam epitaxy (MBE) process. However in this paper, we first propose a NDR circuit composed of standard Si-based metal–oxide–semiconductor field-effect transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT). Then we demonstrate the inverter, NAND, and NOR gate operations using this MOS–HBT–NDR-based MOBILE circuit. The great advantage of this NDR-based application is that we can implement it using the standard SiGe BiCMOS process without the need for the MBE system.     

A high-speed frequency divider using n+-Ge Gate AlGaAs/GaAs MISFET's

A high-speed divide-by-four static frequency divider is fabricated using n+ -Ge gate AlGaAs/GaAs heterostructure MISFET's. The divider circuit consists of two master-slave T-type flip-flops (T-FF's) and an output buffer based on source-coupled FET logic (SCFL). A maximum toggle frequency of 11.3 GHz with a power dissipation of 219 mW per T-F/F is obtained at 300 K using 1.0-µm gate FET's.     

基于RTD的新型全加器设计

单双稳态转换逻辑单元(MOBILE)是基于共振隧穿二极管(RTD)电路的一个重要逻辑单元,非常适合阈值逻辑电路设计。由MOBILE可以构成阈值逻辑门(TG)和广义阈值逻辑门(GTG)等阈值逻辑电路。本文通过将三变量异或函数转化为较简单、理想的GTG输入输出函数形式,设计了由GTG构成的新型三变量异或门,并利用该三变量异或门设计了新型的全加器。通过HSPICE仿真和性能比较,该全加器不仅器件数量少,输出延时短,而且能达到较高的工作频率、更小的电路功耗与功耗-延迟积。     

A high-speed HEMT 1.5K gate array

A 1.5K-gate HEMT gate array has been developed, using a direct-coupled FET logic (DCFL) circuit. The chip, containing 1520 basic cells and 72 I/O cells, was 5.5 mm × 5.6 mm. The basic circuit was designed for two different threshold voltages for D-HEMT, in order to obtain high-speed performance both at room temperature and low temperature. Fully functional 8 × 8 bit parallel multipliers were fabricated on the gate-array chip. At room temperature a multiplication time of 3.7 ns including I/O buffer delay was achieved with power dissipation of 6.0 W at a supply voltage of 1.6 V, and at liquid-nitrogen temperature multiplication time was 3.1 ns where the supply voltage was 0.95 V and the power dissipation was 3.2 W.     

A gallium arsenide SDFL gate array with on-chip RAM

A GaAs gate array has been fabricated featuring 432 SDFL cells, 32 interface I/O buffer cells, and four 4 × 4 bit static RAM's. Each Schottky diode field-effect transistor logic (SDFL) cell can be programmed with 3 options as an unbuffered or buffered NOR gate, or as a dual OR/NAND gate. The interface I/O cell can be programmed for ECL, TTL, CMOS, and SDFL logic families. Each 16 bit RAM is fully decoded using depletion mode MESFET's with SDFL circuit approach. The chip size is 147 mils × 185 mils, and the total power dissipation of the whole chip is less than 3 W. Testing of the cell array has given yields of 70 percent for the 101-stage ring oscillators and about 90 percent for the I/O buffers, memory cells, and 25-stage ring oscillators in a wafer. The best speed performance of the unbuffered SDFL gate is 150 ps for fan-out and fan-in of 1 and the load of 100 µm of interconnect. The average power of the SDFL gate is 1.5 mW. The results demonstrated the feasibility of the GaAs SDFL for fast gate array and memory applications.     

一种基于单电子隧穿结和MOS晶体管的混合随机数发生器

提出了一种新颖的单电子随机数发生器(RNG).该随机数发生器由多个单电子隧穿结(MTJ)以及单电子晶体管(SET)/MOS管混合输出电路组成.MTJ被用于实现一个高频率的振荡器.它利用了电子隧穿的物理随机性得到了很大的振荡频率漂移.SET/MOS管输出电路放大并输出MTJ振荡器的输出信号.该信号经过一个低频信号采样后,产生随机数序列.所提出的随机数发生器使用简单的电路结构产生了高质量的随机数序列.它具有简单的结构,输出随机数的速度可以高达1GHz.同时,该电路还具有带负载能力以及很低的功耗.这种新颖的随机数发生器对未来的密码和通讯系统具有一定的应用前景.     

Analysis of transient response and operating speed of MOBILE

To clarify the relationship between the figures-of-merit of resonant tunneling diodes and the operating speed of a monostable-bistable transition logic element (MOBILE), we investigated the transient response of a MOBILE using a simple current-voltage characteristics model. We found that an unstable point in a MOBILE affects its operation, and false operation occurs when the amplitude of the clock signal is inappropriate. From a calculation of transient time using peak-to-valley current ratio (PVR) and peak current density (j/sub P/) as parameters, we also discovered that a sufficiently high j/sub P/ and higher PVR (>6) are necessary for high-speed operations.     

谐振隧穿晶体管数字单片集成电路

阐述了谐振隧穿器件构成的与非门、单/双稳逻辑转换电路、或非门、流水线逻辑门、D触发器、静态存储器、多值逻辑和静态分频器等数字单片集成电路,它们具有高频高速、低功耗、多值逻辑、节点少、节省器件、简化电路等显著优势,将是数字集成电路后续小型化最有希望的代表。指出材料生长和芯片工艺制作等问题是其实现工业化生产的瓶颈。综述了国内外在该领域的研究现状和发展趋势,特别是美国已经有高水平的谐振隧穿晶体管数字单片电路问世,我国正在开展少量的研究工作。     

一种基于单电子隧穿结和MOS晶体管的混合随机数发生器

提出了一种新颖的单电子随机数发生器(RNG).该随机数发生器由多个单电子隧穿结(MTJ)以及单电子晶体管(SET)/MOS管混合输出电路组成.MTJ被用于实现一个高频率的振荡器.它利用了电子隧穿的物理随机性得到了很大的振荡频率漂移.SET/MOS管输出电路放大并输出MTJ振荡器的输出信号.该信号经过一个低频信号采样后,产生随机数序列.所提出的随机数发生器使用简单的电路结构产生了高质量的随机数序列.它具有简单的结构,输出随机数的速度可以高达1GHz.同时,该电路还具有带负载能力以及很低的功耗.这种新颖的随机数发生器对未来的密码和通讯系统具有一定的应用前景.     

Weighted sum threshold logic operation of MOBILE(monostable-bistable transition logic element) using resonant-tunnelingtransistors

The functional operation of the MOBILE (monostable-bistable transition logic element) has been studied using multiple-input logic gates. The MOBILE uses two resonant-tunneling transistors (RTTs) connected in series and driven by an oscillating bias voltage to produce a mono-to-bistable transition of the circuit. A MOBILE having three input gates with a 1:2:4 width ratio can distinguish all 8 (2³) input patterns corresponding to each weighted sum, depending on the threshold value selected by the control gate. The results confirm the realization of the weighted sum threshold logic operation of input signals