TD-SCDMA中(2,1,9)卷积编码及其VITERBI译码算法的SIMULINK S-FUNCTION实现

文章提出了TD-SCDMA系统中一种(2,1,9)卷积编码及其Viterbi译码的软件实现方案,在Matlab/Simulink平台中应用S-Function实现了(2,1,9)卷积码的Viterbi译码器功能.测试证明,该Viterbi译码器输出的信息比特误码率在低信噪比下仍能达到0.0583.     

高阶调制系统中Viterbi译码的改进算法

本文分析了高阶调制通信系统中将解调和卷积码的译码联合的解码方法,并与传统的Viterbi软判决译码和Viterbi硬判决译码算法进行了比较.仿真结果表明,在不增加复杂度和保持相同的误码率的条件下系统所需信噪比比Viterbi软判决译码降低0.2-0.3dB.本文给出的方法也可推广到更高阶调制通信系统中.     

(2,1,7)卷积编码及其维特比译码算法的软件实现

提出了一种（2，1，7）卷积编码及其维特（Viterbi）译码的软件实现方案，在Matlab环境中应用软件技术实现了（2，1，7）卷积码的Viterbi译码器功能。测试证明，该Viterbi译码算法在低信噪比下的误码率仍能达到10^-6。     

改进型全并行Viterbi译码器设计与实现

卷积码作为一种重要的前向纠错信道编码方式,广泛应用于现代无线通信系统之中。Viterbi译码方式在约束长度较小的前提下能够最大限度地发挥出卷积码的优异性能。对(2,1,5)最佳非系统卷积码的Viterbi译码器的误码率进行了Matlab仿真。针对传统Viterbi译码设计上的不足进行了改进和优化,给出了硬件实现的逻辑原理框图,并利用EDA设计工具基于FPGA来设计实现Viterbi译码模块。最后分析了译码器综合后的资源占用情况并通过时序仿真验证了译码可靠性。     

基于FPGA的卷积码的编/译码器实现

首先阐述了（2,1,2）卷积码的原理和维特比（Viterbi）译码的实现过程,并对编码器、Viterbi译码器进行了现场可编程门阵列（FPGA）设计和实现。仿真表明了设计模块的正确性,而且能够满足速度和精度的要求。其次对最大自由距离的非恶性卷积码在高斯白噪声（AWGN）信道下的误码率性能进行分析,通过Matlab仿真表明卷积码具有很强的纠错能力,当卷积码的约束长度增大时,其误码率逐渐降低。结果表明所设计的卷积码译码器输出时延小,占用资源较少。具有一定的实用价值。     

卷积编码及Viterbi解码的FPGA实现及应用

卷积码在现代无线通信系统中应用十分广泛,Viterbi译码是最常用的一种对卷积码的译码算法。介绍了卷积编码及Viterbi串行解码的原理及其FPGA的实现。在保证系统性能的前提下讨论了分帧式编解码在实际系统中的应用。     

Viterbi解码器RTL级设计优化

当今芯片产业竞争激烈,速度低、面积大、功耗高的产品难以在市场中占有一席之地。Viterbi解码器作为一种基于最大后验概率的最优化卷积码解码器,被广泛应用于多种数字通信系统中,却由于其较高算法复杂程度,给芯片设计带来了挑战。针对芯片的速度、面积和功耗,通过对Viterbi解码器RTL级设计的若干优化方法进行研究和讨论,实现了一个应用于DVB-S系统的面积约为2万门的Viterbi解码器。     

Viterbi译码的FPGA免回溯实现

卷积码在多种通信领域中广泛应用,Viterbi译码是对卷积码的一种最大似然译码算法。随着卷积码约束度的增加,并行维特比译码所需的硬件资源呈指数增长,限制其硬件实现。介绍了一种串行译码结构的FPGA实现方案,在保证性能译码的前提下有效地节省资源。同时提出了充分利用FPGA的RAM存储单元的免回溯Viterbi解码实现算法,减少了译码时延,这种算法在串行和并行译码中都可以应用。     

一种高速Viterbi译码器的设计与实现

Viterbi算法是卷积码的最优译码算法.设计并实现了一种高速(3,1,7)Viterbi译码器,该译码器由分支度量单元(BMU)、加比选单元(ACSU)、幸存路径存储单元(SMU)、控制单元(CU)组成.在StratixⅡ FPGA上实现、验证了该Viterbi译码器.验证结果表明,该译码器数据吞吐率达到231Mbit/s,在加性高斯白噪声(AWGN)信道下的误码率十分接近理论仿真值.与同类型Viterbi译码器比较,该译码器具有高速、硬件实现代价低的特点.     

卷积码编码器和Viterbi译码器的FPGA实现

介绍了目前在数字无线通信中常用的一种向前纠错编码卷积码编码和Viterbi解码的原理，并采用TOP-DOWN的设计思想，利用相关的EDA工具软件进行设计。并将卷积码编码器、Viterbi译码器设计下载到Altera公司的FPGA芯片上进行仿真，得到了预期的设计结果。     

低复杂度的TBCC自适应循环VA译码算法

咬尾是一种将卷积码转换为块码的技术,它消除了归零状态所造成的码率损失,同时避免了截尾带来的性能降低,在短块编码中具有明显优势。针对咬尾卷积码(TBCC)现有译码算法复杂度过大和收敛性问题,提出一种低复杂度的TBCC自适应循环维特比(VA)译码算法。该算法根据信道变化自适应调整译码迭代次数,使咬尾路径收敛到最佳。通过仿真对比不同译码算法的块错误率和译码迭代次数,结果表明TBCC性能明显好于传统卷积码;相比于同类循环VA算法,在不降低性能的前提下,改进算法简化了停止规则,减少译码迭代次数和复杂度,在低信噪比时,改进算法比传统绕维特比译码算法(WAVA)平均迭代次数减少约4次。      

A Novel Parallel Viterbi Decoding Scheme for NoC‐Based Software‐Defined Radio System

In this paper, a novel parallel Viterbi decoding scheme is proposed to decrease the decoding latency and power consumption for the software‐defined radio (SDR) system. It implements a divide‐and‐conquer approach by first dividing a block into a series of subblocks, then performing independent Viterbi decoding for each subsequence, and finally merging the surviving subpaths into the final path. Moreover, a network‐on‐chip‐based SDR platform is used to evaluate the performance of the proposed parallel Viterbi decoding scheme. The experiment results show that our scheme can speed up the Viterbi decoding process without increasing the BER, and it performs better than the current state‐of‐the‐art methods.     

List Viterbi algorithms for continuous transmission

The conventional list Viterbi algorithm (LVA) produces a list of the L best output sequences over a certain block length in decoding a terminated convolutional code. We show in this paper that the LVA with a sufficiently long list is an optimum maximum-likelihood decoder for the concatenated pair of a convolutional code and a cyclic redundancy check (CRC) block code with error detection. The CRC is used to select the output. New LVAs for continuous transmission are proposed and evaluated, where no termination bits are required for the convolutional code for every CRC block. We also present optimum and suboptimum LVAs for tailbiting convolutional codes. Convolutional codes with Viterbi decoding were proposed for so-called hybrid in band on channel (hybrid IBOC) systems for digital audio broadcasting compatible with the frequency modulation band. For high-quality audio signals, it is beneficial to use error concealment/error mitigation techniques to avoid the worst type of channel errors. This requires a reliable error flag mechanism (error detection feature) in the channel decoder. A CRC on a block of audio information bits provides this mechanism. We demonstrate how the LVA can significantly reduce the flag rate compared to the regular Viterbi algorithm (VA) for the same transmission parameters. At the expense of complexity, a receiver optional LVA can reduce the flag rate by more than an order of magnitude. The difference in audio quality is dramatic. The LVA is backward compatible with a VA     

Bit error probability calculations for convolutional codes withshort constraint lengths on very noisy channels

A technique for estimating convolutional code performance on very noisy channels is considered. Specifically, the performance of short constraint length codes operating near the channel cutoff rate is estimated. Decoding convolutional codes with a sliding window decoder (SWD) are considered. This decoder is an optimal (maximum likelihood) symbol decoder as the window size grows toward infinity, while the Viterbi decoder is the maximum-likelihood sequence estimator. The difference in the decoded BERs (bit error rates) between the two decoders is very small and approaches zero asymptotically as the channel BER decreases. Therefore, an estimate on the decoded BER for the SWD can also be used as an estimate of the decoded BER for Viterbi decoding