Influence of solder bump arrangements on molded IC encapsulation

This paper presents a fluid–structure interaction (FSI) analysis of ball grid array (BGA) package encapsulation. Real-time and simultaneous FSI analysis is conducted by using finite volume code (FLUENT) and finite element code (ABAQUS), which are coupled with MpCCI. A BGA integrated circuit (IC) package with different solder bump arrangements is considered in this study. In the FSI analysis, effects of solder bump arrangements on pressure distribution, void, deformation, and stress imposed on the IC structures are investigated. The maximum deformation and maximum stress on the silicon chip and solder bumps are evaluated. The findings indicate that the full-array solder bump package encounters lower stress and deformation during encapsulation. The void formation of each solder bump arrangement is examined. Scaled-up encapsulation is performed and the predicted flow front advancements are substantiated by experimental results. Results demonstrate the excellent capability of the proposed modeling tools for predictive trends of IC encapsulation. Thus, better understanding of IC encapsulation is provided to engineers and package designers in the microelectronics industry.     

电容式微机械超声换能器封装设计

针对电容式微机械超声换能器(CMUT)封装材料阻抗匹配失衡,应力大及声波能量损失大等问题,设计了一种在水下10m透声性能好、弯曲形变小的聚氯乙烯封装结构。依据透声理论和材料属性,计算封装结构参数。利用COMSOL Multiphysics 5.0建立封装结构三维有限元模型,通过模态分析和静态分析分别得到封装结构的固有属性和水下机械性能。封装结构的一阶共振频率为792.47Hz,不会对CMUT 400kHz的工作频段产生干扰。利用压力平衡装置保护水下系统安全性,水下10m最大形变为1.12mm,最大应力为14.4 MPa,未超过聚氯乙烯的弯曲强度。实际测试声压与理论值最大误差为4.8%,物距测量误差为1mm,设计的CMUT封装结构满足设计要求。     

Recent fluid–structure interaction modeling challenges in IC encapsulation – A review

The rapid development of computing software has facilitated multifarious research in integrated circuit (IC) packaging. Complicated and complex processes can be visualized via simulation modeling with this software. The applications of aided software enhance the fundamental physicochemical understanding and visualization of the IC encapsulation process. In this article, fluid–structure interaction (FSI) during IC encapsulation through computer-aided simulation is reviewed based on the amount of substantial work conducted from the past decades to the present. FSI phenomena in various IC encapsulations, such as wire sweep, paddle shift, lead frame deformation, IC chip, and through-silicon via (TSV) deformation, is considered in the review. The significance and challenges of FSI analysis are also highlighted in this article.     

叠层CSP芯片封装热应力分析与优化

对四层叠层CSP（SCSP）芯片封装器件,采用正交试验设计与有限元分析相结合的方法研究了芯片和粘结剂——8个封装组件的厚度变化在热循环测试中对芯片上最大热应力的影响．利用极差分析找出主要影响因子并对封装结构进行优化。根据有限元模拟所得结果．确定了一组优选封装结构,其Von Mises应力值明显比其它组低,提高封装器件的可靠性。     

Strength evaluation of silicon die for 3D chip stacking packages using ABF as dielectric and barrier layer in through-silicon via

The objective of this study is to evaluate the strength of silicon dies covered with a polymer film - Ajinomoto Build-up Film (ABF) - through the four-point bending (4PB) test and finite element method (FEM) analysis. With the evaluated strength, the possibility of die-cracking in 3D packages, wherein the thinned stacking dies are covered with ABF, under a thermal cycle condition is further investigated. In this study, a sandwich structure composed of an ABF layer as the intermediate layer between two (1 0 0) silicon substrates is applied in the 4PB test. Additionally, two kinds of bonding pressure are applied in the fabrication of 4PB specimens: 1 and 5 MPa. The force-displacement relation of the specimen is first measured by the 4PB test. On the other hand, the corresponding FEM model is simulated to obtain the relation of the first principal stress and the applied displacement. By comparing the experimental data and simulation results, the strength of the silicon substrate covered with ABF can be evaluated. Moreover, the FEM analysis results of a 10-layered die stacking 3D package show that the stress distribution in each stacking die does not exceed the evaluated strength. In summary, this paper demonstrates that the strength of the silicon substrate covered with soft and elastic material, such as ABF, as dielectric and barrier layer in 3D die stacking packages can be enhanced.     

Simulations and experiments of three-dimensional paddle shift for IC packaging

Paddle shift is one of the most serious defects which may arise during the IC encapsulation of leadframe-type packages. The term “paddle shift” means the deflection of the leadframe-pad and die as a result of the pressure difference between the top and bottom mold cavities. In extreme cases, paddle shift could lead to a substantial reduction in the reliability of package.This paper employed a computational approach to predict the paddle shift quantity during the IC packaging process. The approach was based on precise finite element (FE) models and flow-structure decoupled analyses. Two kinds of FE models were needed for the decoupled analyses, namely a 3D FE model for the mold filling analysis (i.e. fluid-flow mesh) and a 3D FE model for the structural analysis (i.e. paddle mesh). The aim of the mold filling analysis was to identify the pressure distribution acting on the paddle structure during the encapsulation process, while the objective of the structural analysis was to determine the amount of paddle shift which was caused by pressure distribution.To investigate the relationship between the package geometry and the amount of paddle shift, the present simulations considered six TQFP (Thin quad flat package) models with different geometrical parameters. The simulation results for the paddle shift were compared with the experimental results to demonstrate the accuracy of the proposed numerical approach. It was found that a good agreement exists between the two sets of results.     

LQFP和eLQFP热机械可靠性的有限元分析

封装形式的差异性对产品可靠性具有重要影响。基于有限元法,对比分析了薄型四方扁平封装(LQFP)和载体外露薄型四方扁平封装(eLQFP)在室温和回流焊温度下的翘曲、芯片和粘片胶的应力水平以及各材料界面应力分布。研究表明,LQFP的翘曲比eLQFP的大,但芯片和粘片胶上的最大应力无明显差别;eLQFP在塑封材料与芯片有源面界面的应力水平比LQFP的大;eLQFP在芯片与粘片胶界面、粘片胶与芯片载体界面的剪切应力比LQFP的大,但eLQFP在芯片与粘片胶界面、粘片胶与芯片载体界面的剥离应力比LQFP的小;eLQFP在塑封材料与芯片载体镀银区界面的应力水平高于LQFP的应力水平,由于塑封材料与镀银芯片载体的结合强度弱,eLQFP更易发生界面分层。     

Stress analysis in silicon die under different types of mechanical loading by finite element method (FEM)

Stress analysis is of crucial importance in the design of components and systems in the electronics industry. In this paper, the authors present a new strength criterion combined with finite element analysis (FEA) to predict the failure stress of silicon die. Several different models of pushers were designed to apply load in the vfBGA reliability test until some units failed the electrical test. Meanwhile, finite element analysis was performed in order to find the location of the highest stress and the expected modes of failure. In the simulation, a parametric study of the effect of different types of pushers on the internal stress of the die is carried out and the failure stress can be determined eventually. The potential for chip damage under certain pushers during electrical tests has been assessed and the relationship between the maximum principal stress and the thickness of the silicon die is also explored.     

Investigation of the fluid/structure interaction phenomenon in IC packaging

In the present study, experiment and simulation studies were conducted on the fluid/structure interaction (FSI) analysis of integrated circuit (IC) packaging. The visualisation of FSI phenomenon in the actual package is difficult due to limitations of package size, available equipment, and the high cost of the experimental setup. However, the experimental data are necessary to validate the simulation results in the FSI analysis of IC packaging. Scaled-up package size was fabricated to emulate the encapsulation of IC packaging and to study the effects of FSI phenomenon in the moulded package. The interaction between the fluid and the structure was observed. The deformation of the imitated chip was studied experimentally. The air-trap mechanism that occurred during the experiment is also presented in this paper. Simulation technique was utilised to validate the experimental result and to describe the physics of FSI. The predicted flow front was validated well by the experiment. Hence, the virtual modelling technique was proven to be excellent in handling this problem. The study also extends FSI modelling in actual-size packaging.     

微系统三维(3D)封装技术

文章论述塑料三维(3D)结构微系统封装技术相关问题,描述了把微电机硅膜泵与3D塑料密封垂直多芯片模块封装(MCM-V)相结合的微系统集成化。采用有限元技术分析封装结构中的封装应力,根据有限元设计研究结果,改变芯片载体结构,降低其发生裂纹的危险。计划采用板上芯片和塑料无引线芯片载体的替代低应力和低成本的3D封装技术方案。     

The effect of hygro-mechanical and thermo-mechanical stress on delamination of gold bump

The reliability of the FC–CSP (flip chip–chip scaled package) package with gold bump at the MRT (moisture resistance test) reflow temperature, was evaluated by using the finite element method. The moisture properties of EMC (epoxy molding compound) obtained from the test described in JEDEC standard, were used to characterize the local moisture concentration analysis by transient moisture diffusion, the hygro-mechanical analysis by CME, the vapor pressure analysis and the thermo-mechanical analysis by CTE mismatch. Also, after precondition, the package reliability under the reflow process was predicted, by comparing and integrating each factors, package swelling and stress due to by vapor pressure, as well as thermo-mechanical stress. Consequently, the result showed that the effects on hygro-mechanical stress and vapor pressure in a package could not be negligible, when it is compared with that of the thermo-mechanical stress by CTE mismatch, which is recognized as the main effect on the package crack under reflow temperature. The stress was concentrated at interface between gold bump and die, where most of delamination occurred.     

SCSP中芯片黏结层在焊接时的可靠性

提出了一个细观力学模型,该模型同时考虑了热膨胀和蒸汽膨胀对叠层芯片尺寸封装(SCSP)中芯片黏结层变形的影响.当初始温度确定时,由该模型可求得给定温度下芯片黏结层内部的蒸汽压力和孔隙率,从而判断芯片黏结层在焊接回流时的可靠性.当温度从100℃升高到250℃时,芯片黏结层的饱和蒸汽压、等效弹性模量及孔隙率分别从0.10 ...     

Reliability Study of High-Density EBGA Packages Using the Cu Metallized Silicon

The reliability of high-density enhanced ball grid array (EBGA) packages using the eight-layer Cu metallization silicon was discussed. The key failure mechanisms included the die cracking (in the vicinity of the edge) and thin film delamination. It was noticed that the failure was unique to the Cu metallization silicon. The large package body size (45 mm$^{2}$) and the die size (approximately 15 mm$^{2}$ ) provided additional manufacturing and reliability challenges. The die-edge defects induced during the wafer sawing process were exhibited to be the culprits of the die cracking and the thin film delamination failures. Additionally, the height of die attach fillets significantly influenced the stresses on the die edge, and the excessive fillet height was found to help extend initial cracks at the edge of the silicon. The results demonstrated the adoption of a dual-step wafer sawing scheme and resin blades would control the defects and reduce the failure rate dramatically. A mixture of low-stress encapsulation and die attach materials would help improve the overall reliability of the packages as well. The solder joint reliability of the package was very robust based on the board-level reliability testing results. The statistical analysis of the test results confirmed that most of the die cracking and thin film delamination failures were early-life failures and random. A good sample screening scheme and the process improvement procedure would help improve the reliability and insure the customer a low failure rate for the lifetime of the product. The predicted reliability of the package met the application life needs for the products with process improvement plans in place.      

Stress analysis of 3-dimensional IC package as function of structural design parameters

Solid Liquid Inter-Diffusion (SLID) is a technology that has recently been utilized to fabricate 3D ICs. Since application of this technology is in its infancy stages, manufacturability and reliability of these bonds are still under heavy investigations. This study presents an elastic-plastic finite element and analytical analyses that were implemented to evaluate effect of package design parameters on thermo-mechanical reliability of the SLID bonds and copper interconnects. A numerical experiment is designed in which several design parameters; die thickness, bond size, underfill stiffness and substrate thickness, are varied in 3 levels. Stress in SLID bonds and in copper interconnects were evaluated using the 3-dimensional finite element analysis as well as an analytical approach. The results show that die and substrate thicknesses are the most influential factors among the selected parameters on stress at the interface and on copper interconnects. Main effect results for stress analysis in SLID bonds using finite element shows that die thickness and underfill stiffness are the most influential factors in defining stress at SLID bonds. Results of the analytical approach confirm the finite element analysis. It is shown that effect of interconnect size and pitch is very small compared to die thickness. In average increasing die thickness increases both shear and peeling stresses at the interfaces and copper interconnects.     

Deformation behavior of solid polymer during hot embossing process

Though hot embossing is a well known technique for the fabrication of polymer based micro-device, the deformation behavior of solid polymer during hot embossing process is not investigated clearly. In this paper, the deformation behavior of solid polymer was observed by two methods, synchronous observation and asynchronous analysis. A finite element simulation and a phenomenological model were used to evaluate the deformation behavior of solid polymer during hot embossing. Results showed that the deformation of solid polymer during embossing process included two stages. One was a stress concentration and strain hardening stage, which occurred during the heating and applying pressure process. The “swallowtails” induced by incomplete filling generate at this stage. The other was a stress relaxation and deformation recovery stage, which occurred during the remaining temperature and pressure process. The “swallowtails” were eliminated at this stage. The second stage was significant for improving replication precision, but it had not been reported before.     

叠层CSP封装工艺仿真中的有限元应力分析

叠层CSP封装已日益成为实现高密度、三维封装的重要方法。在叠层CSP封装工艺中,封装体将承受多次热载荷。因此,如果封装材料之间的热错配过大,在芯片封装完成之前,热应力就会引起芯片开裂和分层。详细地研究了一种典型四层芯片叠层CSP封装产品的封装工艺流程对芯片开裂和分层问题的影响。采用有限元的方法分别分析了含有高温过程的主要封装工艺中产生的热应力对芯片开裂和分层问题的影响,这些封装工艺主要包括第一层芯片粘和剂固化、第二、三、四层芯片粘和剂固化和后成模固化。在模拟计算中发现:(1)比较三步工艺固化工艺对叠层CSP封装可靠性的影响,第二步固化工艺是最可能发生失效危险的;(2)经过第一、二步固化工艺,封装体中发现了明显的应力分布特点,而在第三步固化工艺中则不明显。     

Evaluating the material properties of underfill for a reliable 3D TSV integration package using numerical analysis

The effects of the material properties of the underfill layer on thermal stress and deformation in 3D through silicon via (TSV) integration packages were evaluated through numerical analysis. Sample TSV packages with underfill composed of different silica volume ratios were fabricated. The sample packages were used to measure thermal deformation using a Moiré interferometer. Also, a cross-section from these samples was used for 2D finite element modeling and numerical analysis to obtain its thermal deformation. The experimental and numerical results were compared to confirm the suitability of the numerical technique in this research. A four-chip-stacked TSV integration package, which includes underfill layers of four different silica volume ratios, was proposed and designed. The diagonal part of the TSV integration packages were three dimensionally modeled and adopted for numerical analysis. Among the underfill with different silica volume ratios in the designed packages, a silica volume ratio of around 20% shows the best performance for a reliable flip chip bonding process, effectively minimizing thermal stress and deformation in the package.     

CBGA组件热变形的2D-Plane42模型有限元分析

介绍有限元中的2D－Plane42模型在CBGA组件热变形中的应用，利用有限元的模拟CBGA组件的应变、应力的分布，通过模拟表明有限元法是研究微电子封装中BGA焊点、CBGA组件的可靠性的方法。     

3-D packaging methodologies for microsystems

Issues associated with the packaging of microsystems in plastic and three-dimensional (3-D) body styles are discussed. The integration of a microsystem incorporating a micromachined silicon membrane pump, into a 3-D plastic encapsulated vertical multichip module package (MCM-V) is described. Finite element techniques are used to analyze the encapsulation stress in the structure of the package. Cracks develop in the chip carrier due to thermomechanical stress. Based on the results of a finite element design study, the structures of the chip carriers are modified to reduce their risk of cracking. Alternative low stress 3-D packaging methodologies based on chip on board and plastic leadless chip carriers are discussed.     

功率载荷下叠层芯片封装的热应力分析和优化

应用有限元分析软件ANSYS,模拟功率载荷下叠层芯片封装中芯片温度和应力分布情况,得出芯片的温度、应力与材料厚度、热膨胀系数之间的关系,根据分析,对模型进行了优化.优化后的模型最高温度下降了3.613 K,最大应力下降了33.4%,最大剪应力下降了45.9%.