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对四层叠层CSP(SCSP)芯片封装器件,采用正交试验设计与有限元分析相结合的方法研究了芯片和粘结剂——8个封装组件的厚度变化在热循环测试中对芯片上最大热应力的影响.利用极差分析找出主要影响因子并对封装结构进行优化。根据有限元模拟所得结果.确定了一组优选封装结构,其Von Mises应力值明显比其它组低,提高封装器件的可靠性。 相似文献
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研究了温度循环载荷下叠层芯片封装元件(SCSP)的热应力分布情况,建立了SCSP的有限元模型。采用修正后的Coffin-Masson公式,计算了SCSP焊点的热疲劳寿命。结果表明:多层芯片间存在热应力差异。其中顶部与底部芯片的热应力高于中间的隔离芯片。并且由于环氧模塑封材料、芯片之间的热膨胀系数失配,芯片热应力集中区域有发生脱层开裂的可能性。SCSP的焊点热疲劳寿命模拟值为1 052个循环周,低于单芯片封装元件的焊点热疲劳寿命(2 656个循环周)。 相似文献
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电子设备的封装结构多采用层状排布,封装方式多采用焊接工艺,因此封装体中的电子元件失效形式大多是由于各层封装材料热膨胀性能不匹配,导致开、断开关时焊接点脱落或开裂,进而导致硅芯片工作热量不能通过散热基板扩散至电子设备之外,芯片因工作温度过高而失效。运用ANSYS热分析软件对电子封装结构进行热应力分析发现,温度变化对焊料的脱落、开裂造成显著影响。根据热分析结果,提出有关焊料厚度及封装材料性能的改进意见,这样既节约实验成本,又能有效缩短研究电子封装可靠性及电子设备使用寿命的时间。 相似文献
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采用通用有限元软件MSC.Marc,模拟分析了一种典型的多层超薄芯片叠层封装器件在经历回流焊载荷后的热应力及翘曲分布情况,研究了部分零件厚度变化对器件中叠层超薄芯片翘曲、热应力的影响。结果表明:在整个封装体中,热应力最大值(116.2 MPa)出现在最底层无源超薄芯片上,结构翘曲最大值(0.028 26 mm)发生于模塑封上部边角处。适当增大模塑封或底层无源芯片的厚度或减小底充胶的厚度可以减小叠层超薄芯片组的翘曲值;适当增大底层无源超薄芯片的厚度(例如0.01 mm),可以明显减小其本身的应力值10 MPa以上。 相似文献
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采用有限元方法,建立了功率器件封装的三维有限元模型,分析了封装体的温度场和应力场,讨论了芯片粘贴焊层厚度、空洞等因数对大功率器件封装温度场和应力场的影响.有限元结果表明,封装体的最高温度为73.45℃,位于芯片的上端表面,焊层热应力最大值为171 MPa,出现在芯片顶角的下面位置.拐角空洞对芯片最高温度影响最大,其次是中心空洞.空洞沿着对角线从中点移动到端点,芯片最高温度先减小后增加.焊层最大热应力出现在拐角空洞处,最大值为309 MPa.最后分析了芯片粘贴工艺中空洞形成的机理,并根据有限元分析结论对工艺的改善优化提出建议. 相似文献
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随着电子封装微型化、多功能化的发展,三维封装已成为封装技术的主要发展方向,叠层CSP封装具有封装密度高、互连性能好等特性,是实现三维封装的重要技术。针对超薄芯片传统叠层CSP封装过程中容易产生圆片翘曲、金线键合过程中容易出现0BOP不良、以及线孤(wireloop)的CPK值达不到工艺要求等问题,文中简要介绍了芯片减薄方法对圆片翘曲的影响,利用有限元(FEA)的方法进行芯片减薄后对悬空功能芯片金线键合(Wirebond)的影响进行分析,Filmon Wire(FOW)的贴片(DieAttach)方法在解决悬空功能芯片金线键合中的应用,以及FOW贴片方式对叠层CSP封装流程的简化。采用FOW贴片技术可以达到30%的成本节约,具有很好的经济效益。 相似文献
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本文对八层叠层CSP封装器件进行热应力分析。结果表明,热应力集中出现在上层芯片(die8)、die7的悬置端和底层芯片(die1)与粘结剂的边角处。进一步,采用响应曲面法(RSM)与有限元分析相结合的方法研究die8、die7、die1和粘结剂厚度对器件热应力的影响。应用响应曲面法优化芯片和粘结剂的厚度以得到最小VonMises应力,其结果为106.87Mpa。与初始设计时的应力值143.9Mpa相比减小了25.7%。应力减小有助于提高封装产品的可靠性。 相似文献
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The modified J-integral and the stress intensity factor based on linear elastic fracture mechanics can be applied to predict the growth of interfacial delamination in integrated circuit (IC) packages. One of the key parameters required is the interfacial fracture toughness. This paper describes the measurement of the interfacial fracture toughness as a function of temperature and relative humidity using a three-point bending test. The interfacial fracture toughness was found to decrease with temperature and relative humidity. It is proposed that delaminations propagate from very small voids or defects present at the interface. The effect of the location of these interfacial defects or cracks on delamination was studied. The IC package evaluated in this paper was an 80-pin quad flat package with a 0.2 mm defect or crack at the edge or at the center of the interface. It was found that as the temperature of the package was increased, the stress intensity factor of the edge crack was higher than that of the center crack. However, whether the edge crack will propagate first as temperature is increased depends on the ratio of mode II interface toughness to that of the mode I interface toughness. For the package under investigation, it was established that when this ratio is less than 2.69 the edge crack would propagate first, otherwise the center crack would. For small defects, it was found that the water vapor pressure developed at the interface did not have a significant effect on the value of the crack-tip stress intensity factor 相似文献
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Impact of flip-chip packaging on copper/low-k structures 总被引:1,自引:0,他引:1
Mercado L.L. Kuo S.-M. Goldberg C. Frear D. 《Advanced Packaging, IEEE Transactions on》2003,26(4):433-440
Copper/low-k structures are the desired choice for advanced integrated circuits (ICs). Nevertheless, the reliability might become a concern due to the considerably lower strength and greater coefficient of thermal expansion (CTE) of the low-k materials. To ensure successful integration of the new chips within advanced packaging products, it is essential to understand the impact of packaging on chips with copper/low k structures. In this study, flip-chip die attach process has been studied. Multilevel, multiscale modeling technique was used to bridge the large gap between the maximum and minimum dimensions. Interface fracture mechanics-based approach has been used to predict interface delamination. Both plastic ball grid array (PBGA) and ceramic ball grid array (CBGA) packages were evaluated. Critical failure locations and interfaces were identified for both packages. The impact of thin film residual stresses has been studied at both wafer level and package level. Both PBGA and CBGA packaging die-attach processes induce significantly higher crack driving force on the low-k interfaces than the wafer process. CBGA die-attach might be more critical than PBGA die-attach due to the higher temperature. During CBGA die-attach process, the crack driving force at the low-k/passivation interface may exceed the measured interfacial strength. Two solutions have been suggested to prevent catastrophic delamination in copper/low-k flip-chip packages, improving adhesion strength of low-k/barrier interface or adding tiles and slots in low-k structures to reduce possible area for crack growth. 相似文献