微波退火法制备多晶硅薄膜的电学特性研究

为实现多晶硅薄膜晶体管有源矩阵液晶显示器的实用化与产业化 ,低温 (<6 0 0°C)、快速制备高质量多晶硅薄膜已成为研究热点。文中将微波加热技术应用于金属诱导 a- Si薄膜横向晶化工艺中 ,成功实现了低温快速制备多晶硅薄膜。通过薄膜电阻率的测试 ,分析了多晶硅薄膜的电学特性。     

多晶硅有源矩阵液晶显示器

本文首先就用来制造有源矩阵液晶显示器的非晶硅和多晶硅材料作了性能比较,然后描述了多晶硅薄膜晶体管阵列的制造方法,以及在制造方法上取得的进展。     

有源矩阵液晶显示集成驱动电路

介绍了多晶硅薄膜晶体管的特性,分析了有源矩阵液晶显示的扫描和数据驱动电路,以及用于多晶硅薄膜晶体管的集成驱动电路的设计方案。     

Poly—Si TFT制备工艺

在有源矩阵液晶显示中，目前倍受重视的应数多晶硅有源矩阵液晶显示技术，本文较详细地给出了高温多晶硅薄膜晶体管的制备工艺及其特性，并分析讨论了制备条件对多晶硅薄膜晶体管各种参数的影响。     

低温金属诱导横向晶化多晶硅材料和器件技术

使用金属镍诱导非晶硅晶化(MIC:metal-induced crystallization)技术,获得了低温(＜550℃)多晶硅.通常在镍覆盖区以外的晶化硅更加有用,这一技术被称为金属诱导横向晶化(MILC:metal-induced lateral crystallization)技术.通过对结晶动力学过程和材料特性的研究,提出了可同时适用于镍覆盖区和相连非覆盖区金属诱导结晶的同一晶化机制.虽然MILC多晶硅的材料特性明显优于固相晶化多晶硅的材料特性,薄膜晶体管沟道中存在MIC/MILC 的界面所形成的横向晶界会明显的降低其性能.若将这些界面从沟道中去除掉,即可获得可满足液晶和有机发光二极管等显示器进行系统集成所需的高性能器件.     

晶化前后有源层的刻蚀对poly—Si TFT性能的影响

在普通玻璃衬底上低温（600度以下）制备poly-Si TFT有源矩阵液晶显示器是当前的研究热点,采用金属诱导横向晶化法低温研制了poly-Si TFT。分析了晶化前后有源层的刻蚀有poly-Si TFT性能的影响。     

晶化前后有源层的刻蚀对poly-Si TFT性能的影响

在普通玻璃衬底上低温 ( 6 0 0℃以下 )制备 poly SiTFT有源矩阵液晶显示器是当前的研究热点。采用金属诱导横向晶化法低温研制了 poly SiTFT。分析了晶化前后有源层的刻蚀对poly SiTFT性能的影响。     

薄膜单晶硅有源矩阵液晶显示器

从分析有源矩阵液晶显示器的发展形势出发，着重介绍了薄膜单晶硅有源矩阵液晶显示器的优势和和制作过程，指出这种显示器目前有投影显示和小尺寸显示方面有较好的市场前景。     

微波退火法低温制备多晶硅薄膜晶体管

多晶硅薄膜晶体管以其独特的优点在液晶显示领域中有着重要位置。为了满足在普通玻璃衬底上制备多晶硅薄膜晶体管有源矩阵液晶显示器,低温制备（小于600℃）高质量多晶硅薄膜已成为研究热点,文章利用微波加热技术,采用非晶硅薄膜微波退火固相晶化法低温制备出多晶硅薄膜晶体管,研究了微波退火工艺对多晶硅薄膜晶体管电学性能的影响。     

MIUC poly-Si TFT显示驱动电路的性能优化

以金属诱导单向横向晶化多晶硅薄膜晶体管(MIUC poly-Si TFT)为基本器件单元,采用2M1P 5 μmCMOS工艺研制出适合于作全集成有源显示周边驱动的行扫描和列驱动电路.行扫描和列驱动电路的工作频率随工作电压呈指数式增加,然后趋于线性增长.在外加激励信号电压为10 V时,工作频率可以达5 MHz.在5 V电压应力条件下连续工作15000 s,行扫描和列驱动电路的输出特性基本不衰退.将这样的行、列驱动电路集成制作于像素矩阵电路的周边,研制出具有良好动态显示功能的彩色"板上系统(SOP)"型有源选址液晶显示器(AMLCD)模块.     

High-performance polycrystalline silicon thin-film transistor technology using low-temperature metal-induced unilateral crystallization

Low-temperature metal-induced unilaterally crystallized polycrystalline silicon thin-film transistors (TFTs) have been developed and characterized. These TFTs are better than their solid-phase crystallized counterparts in many process and device performance measures, such as shorter and simpler process flow, higher field-effect mobility, reduced leakage current, better immunity to early drain breakdown and much improved spatial uniformity of device parameters. They have been used to realize active matrices for liquid-crystal (LC) and organic light-emitting diode (OLED) flat-panel displays.     

High performance low temperature metal-induced unilaterallycrystallized polycrystalline silicon thin film transistors forsystem-on-panel applications

Thin film transistors (TFTs) with low-temperature processed metal-induced laterally crystallized (MILC) channels and self-aligned metal-induction crystallized (MIC) source and drain regions have been demonstrated recently as potential devices for realizing electronics on large-area, inexpensive glass panels. While these TFTs are better than their solid-phase crystallized counterparts in many device performance measures, they suffer from higher off-state leakage current and early drain breakdown. A new technology is proposed, employing metal-induced-unilateral crystallization (MIUC), which results in the removal from the edges of and within the channel region all major grain boundaries transverse to the drain current flow. Compared to the conventional “bilateral” MILC TFTs, the new MIUC devices are shown to have higher field-effect mobility, significantly reduced leakage current, better immunity to early drain breakdown, and much improved spatial uniformity of the device parameters. Thus they are particularly suitable for realizing low temperature CMOS systems on inexpensive glass panels     

An empirical model to determine the grain size of metal-induced lateral crystallized film

Thin-film transistors (TFTs) have been fabricated using the nickel-seeded metal-induced lateral crystallization (MILC), in which an amorphous silicon is crystallized to form a large grain polysilicon film. Single crystal SOI, solid phase crystallization (SPC), and MILC TFTs were fabricated and the carrier mobilities extracted. Different types of devices have different variations in electrical properties. An empirical model based on the presence of the grain boundaries is proposed to explain the experimental results. The experimental data was used to extract the model parameters and the number of grains and grain size present in the device channel. The results can be further used to optimize the crystallization process and the device design.     

Polycrystalline silicon thin-film transistors with two-stepannealing process

Thin-film transistors (TFTs) were fabricated from poly-Si crystallized by a two-step annealing process on glass substrates. The combination of low-temperature furnace annealing and high-temperature rapid thermal annealing leads to a significant improvement in the material quality. The TFTs obtained with this two-step annealing material exhibit better measured characteristics than those obtained by using conventional furnace annealing     

Thin-film transistors fabricated with poly-Si films crystallized atlow temperature by microwave annealing

Solid phase crystallization of amorphous silicon films for poly-Si thin film transistors (TFTs) has advantages of low cost and excellent uniformity, but the crystallization temperature is too high. Using a microwave annealing method, we lowered the crystallization temperature and shortened the crystallization time. The complete crystallization time at 550°C was within 2 h. The device parameters of TFTs with the poly-Si films crystallized by microwave annealing were similar to those of TFTs with the poly-Si films crystallized by conventional furnace annealing. The new crystallization method seems attractive because of low crystallization temperature, short crystallization time, and comparable film properties     

High-performance nonhydrogenated nickel-induced laterally crystallized P-channel poly-Si TFTs

High-performance nickel-induced laterally crystallized (NILC) p-channel poly-Si thin-film transistors (TFTs) have been fabricated without hydrogenation. Two different thickness of Ni seed layers are selected to make high-performance p-type TFTs. A very thin seed layer (e.g., 5 /spl Aring/) leads to marginally better performance in terms of transconductance (Gm) and threshold voltage (V/sub th/) than the case of a 60 /spl Aring/ Ni seed layer. However, the p-type poly-Si TFTs crystallized by the very thin Ni seeding result in more variation in both V/sub th/ and G/sub m/ from transistor to transistor. It is believed that differences in the number of laterally grown polycrystalline grains along the channel cause the variation seen between 5 /spl Aring/ NILC TFTs compared to 60-/spl Aring/ NILC TFTs. The 60 /spl Aring/ NILC nonhydrogenated TFTs show consistent high performance, i.e., typical electrical characteristics have a linear field-effect hole mobility of 156 cm/sup 2//V-S, subthreshold swing of 0.16 V/dec, V/sub th/ of -2.2 V, on-off ratio of >10/sup 8/, and off-current of <1/spl times/10/sup -14/ A//spl mu/m when V/sub d/ equals -0.1 V.     

Fabrication of thin film transistors using a Si/Si1-xGex/Si triple layer film on a SiO2 substrate

A novel approach that can reduce the thermal budget in the fabrication of thin film transistors (TFTs) using a Si/Si_0.7Ge_0.3/Si triple film as an active layer was proposed. The crystallization behavior of the triple film was described and device characteristics of Si/Si_0.7Ge_0.3 /Si TFTs were compared with those of Si TFTs and of SiGe TFTs. The triple film was completely crystallized only after a 25-h anneal at 550°C. N-channel polycrystalline Si/Si_0.7Ge_0.3/Si TFTs had a field-effect mobility of 57.9 cm²/Vs and an I_on/I_off ratio of 5.7×10⁶. This technique provides not only a shorter time processing capability than Si TFT's technology but also superior device characteristics compared to SiGe TFTs     

高温处理对镍诱导晶化硅上的薄膜晶体管性能的影响

采用标准双栅CMOS工艺在镍诱导非晶硅横向晶化形成的多晶硅上制造了高性能的薄膜晶体管,并详细研究了器件制备前高温预处理对薄膜晶体管性能的影响.实验发现不同的温度处理,将引起器件性能的显著变化.在1000℃预处理温度下获得了最好的器件性能.1000℃在NMOS管中测得的电子迁移率达314cm2/(V*s),分别比在1100℃和未做高温处理下的大10%和22%.1000℃下器件的最大开关电流比也达到了3×108.对器件的进一步重复性研究证实了上述结果的可靠性.     

Low-temperature single-crystal Si TFTs fabricated on Si filmsprocessed via sequential lateral solidification

Nonhydrogenated, n-channel, low-temperature-processed, single-crystal Si thin-film transistors (TFTs) have been fabricated on Si thin films prepared via sequential lateral solidification (SLS). The device characteristics of the resulting SLS TFTs exhibit properties and a level of performance that are superior to polycrystalline Si-based TFTs and are comparable to similar devices fabricated on silicon-on-insulator (SOI) substrates or bulk-Si wafers. We attribute these high-performance device characteristics to the absence of high-angle grain-boundaries within the active channel portion of the TFTs