热功率信号下芯片温度动态响应及热特性分析

针对电子元件在瞬态传热中的热惯性问题,对芯片在热功率信号作用下的温度动态响应特性进行识别。根据芯片温度对芯片发热功率的阶跃响应曲线,求得芯片上关键点的传递函数;根据芯片温度的方波响应曲线和正弦响应曲线,重点对热功率信号给芯片造成的温度冲击与信号周期之间的关系进行分析。该研究对提高电子元件抵抗热冲击和热疲劳的能力具有指导意义。     

集成风速计片上系统的计算机模拟

将MEMS器件与CMOS电路集成在同一个芯片上具有体积小、噪声小、便于控制、易于大批量生产等优点 ,本文从风速计的工作场入手 ,运用了有限元、数据拟合、等效电路及SPICE宏单元的方法对片上系统进行模拟 ,从而直接模拟出信号状况 ,有利于片上处理电路和控制电路的匹配设计 ,提高了设计效率。文中给出了风速计流体场的有限元分析结果 ,并通过拟合的方法将输出的温度差输出到电路等效的热堆 ,信号和噪声经过片上集成的放大器输出到芯片外 ,有利于温度场、热敏感元件、放大电路的优化设计     

集成风速计片上系统的计算机模拟

将MEMS器件与CMOS电路集成在同一个芯片上具有体积小、噪声小、便于控制、易于大批量生产等优点,本文从风速计的工作场入手,运用了有限元、数据拟合、等效电路及SPICE宏单元的方法对片上系统进行模拟,从而直接模拟出信号状况,有利于片上处理电路和控制电路的匹配设计,提高了设计效率.文中给出了风速计流体场的有限元分析结果,并通过拟合的方法将输出的温度差输出到电路等效的热堆,信号和噪声经过片上集成的放大器输出到芯片外,有利于温度场、热敏感元件、放大电路的优化设计.     

一种VLSI热载流子退化的嵌入式实时预测方法

提出了一种VLSI热载流子退化的嵌入式实时预测方法,并在0.18μm CMOS混合信号工艺下完成了预测电路设计。当VLSI热载流子退化引起的瞬态性能退化超过预设的界限时,预测电路会发出一个报警信号。它只占用很小的芯片面积,同时它几乎不与被测电路共用信号(除上电复位信号和电源信号外),从而不会给被测试系统带来任何干扰。     

集成风速计片上系统的计算机模拟

将MEMS器件与CMOS电路集成在同一个芯片上具有体积小、噪声小、便于控制、易于大批量生产等优点，本文从风速计的工作场入手，运用了有限元、数据拟合、等效电路及SPICE宏单元的方法对片上系统进行模拟，从而直接模拟出信号状况，有利于片上处理电路和控制电路的匹配设计，提高了设计效率。文中给出了风速计流体场的有限元分析结果，并通过拟合的方法将输出的温度差输出到电路等效的热堆，信号和噪声经过片上集成的放大器输出到芯片外，有利于温度场、热敏感元件、放大电路的优化设计。     

基于硅虚拟原型的RISC CPU核物理设计

在物理设计前期芯片物理信息供不应求的瓶颈制约着超深亚微米系统芯片设计时序、功率、信号完整性收敛及物理层次化设计方法的有效应用，硅虚拟原型在芯片物理设计流程中的应用有效地解决了这些问题。文章介绍了一个基于SVP的32位RISC CPU核的物理设计实现，并分析讨论了保持SVP与最终实现芯片时序相关性的方法。     

基于FPGA IP核的中频接收与脉压设计

随着FPGA（现场可编程门阵列）在规模和性能上得到显著增强,意味着FPGA能够代替DSP或者某些专用芯片,实现数字信号处理中某些运算密集型的算法,并且能够获得更高的性能。在分析数字正交检波技术和数字脉压技术的基础上,介绍了一种基于FPGA芯片的数字中频接收机设计方案,该接收机能够实现线性调频信号的数字下变频和数字脉压功能。该设计采用FPGAIP核来实现,另外,还介绍了主要IP核的特性,并提出了一些简化方法,用以节约FPGA内部资源提高效率。     

一种基于PCI IP核的码流接收卡的设计

本文介绍了一种基于Altera公司的PCI接口IP核的DVB码流接收系统的硬件设计方案及设计要点的分析。该设计采用Altera公司的新一代FPGA芯片EP1C12和PCIIP核以及高速串行数据通信接收芯片,实现DVB-ASI信号的接收。     

用于混合信号VLSI的可扩展JTAG控制器IP核设计

正电子发射断层成像系统（PET）前端读出电路是数模混合信号超大规模集成电路芯片.针对多通道高性能PET专用集成电路芯片的特点,采用JTAG控制器对该芯片进行初始控制和辅助测试.采用TSMC 0.18μmCMOS工艺设计实现了一个可扩展的JTAG控制器IP核,支持14组可扩展控制信号和16个多位寄存器扫描链的读/写操作,并配备定制的底层驱动软件.该JTAG控制器IP核还可用于其它混合信号VLSI的控制与测试,具有较强的通用性和工程实用价值.     

并发追踪数据流的多缓存选址算法

为了验证多核芯片的正确性,通常需要同时观测不同芯核上的多组信号。如何实时处理并发追踪中多组数据流已经成为多核芯片硅后功能验证所面临的关键挑战之一。本文提出了一种基于映射的自调节缓存选址（M ap-Based Self-Regulation Location Selection ,MSLS）算法,该算法通过优化多缓存选址,在片上网络通信带宽限制下保证了并发追踪数据流能够实时存储,同时降低了追踪数据流传输能耗。实验结果表明了该方法的有效性。     

Fast and accurate thermal modeling and simulation of manycore processors and workloads

Today's microprocessors require careful analysis of their thermal behavior both at design time as well as at runtime. However, accurate prediction of thermal behavior is possible only through simulations due to the complexity and the high dynamicity of their operation. Unfortunately, accurate simulations of such complex systems are computationally intensive, therefore time consuming, while on the other hand, simplified models often cause mispredictions leading to overdesign and lowered performance. In our work, we propose a new discrete-time method of assessment of the run-time temperature of a processor based on an approximation of its instructions-per-cycle (IPC) by a finite Fourier series expansion. Our method is AC-based, and shows significant increase of accuracy in comparison to well-known DC (average)-based models. Furthermore, we provide a new Dynamic Voltage and Frequency Scaling (DVFS) model based on our estimations.     

Fast thermal analysis for fixed-outline 3D floorplanning

Three dimensional integrated circuits (3D ICs) can alleviate the problem of interconnection, a critical problem in the nanoscale era, and are also promising for heterogeneous integration. However, the thermal challenge in industry is one of key obstacles to adopt the 3D ICs technology. Various thermal analysis models for 3D IC have been proposed in literature. However, the long simulation cycle makes runtime of thermal management inefficient during floorplanning phase. In this paper, we propose a fast thermal analysis method for fixed-outline 3D floorplanning. Before floorplanning, we simulate the thermal distribution of each block placed on different positions. Based on the simulated thermal profiles, bilinear interpolation is adopted to quickly estimate temperature during floorplanning. After the block planning, a heuristic method, which combines the shortest path and min-cost-max-flow, is presented for TSV allocation with minimization of chip temperature and wirelength. Compared with the superposition of thermal profiles method, the proposed thermal analysis method can reduce the peak temperature by 6.7% on average with short runtime for 3D fixed-outline floorplanning, which demonstrates the efficiency and effectiveness of the proposed thermal analysis method.     

机载雷达的地图显示技术

介绍了现代机载雷达信号处理机用软件方法实现实波束地图成像的方法,提出了适合于软件实现的坐标变换新方法,并对成像过程中可能出现的漏点、图像不均匀、漏小目标、细节不清等都作了较好处理。该算法具有运算简单、运算时间固定、图像质量高等特点,因而具有较高的使用价值。     

Design of multi-mode application-specific cores based on high-level synthesis

In a mobile society, more and more devices need to continuously adapt to changing environments. Such mode switches can be smoothly done in software using a general purpose processor or a digital signal processor. However hardware cores only can cope with both throughput and power consumption constraints. Reconfigurable hardware platforms provided by FPGA devices offer partial reconfiguration at runtime. However they require too long reconfiguration times and they cannot satisfy mobile device power consumption requirements. In this article we propose a methodology to map selected groups of DSP tasks to multi-mode cores using conventional hardware technologies.     

A Fault Tolerant Approach for FPGA Embedded Processors Based on Runtime Partial Reconfiguration

The ever increasing adoption of field programmable devices in various application domains for building complex embedded systems based on FPGA processors along with the reliability issues having emerged for FPGA devices built with the latest nanometer technologies, have raised the need for new fault tolerant techniques in order to improve dependability and extend system lifetime. In addition, the runtime partial reconfiguration technology highly mature in the modern FPGA families along with the availability of unused programmable resources in most FPGA designs provide new and interesting opportunities to build advanced fault tolerance mechanisms. In this paper, we exploit the dynamic reconfiguration potential of today’s FPGA architectures and the advances in the related design support tools and we propose a fault-tolerant approach for FPGA embedded processors based on runtime partial reconfiguration. According to the proposed methodology, the processor core is partitioned into reconfigurable modules and each module is duplicated to implement a concurrent error detection mechanism. Precompiled configurations containing spare resources are generated for each duplicated module and are used to repair at runtime the defective modules. Also, a fault tolerance scheme for the proxy logic of the reconfigurable modules, which cannot move in the alternative configurations along with the rest logic, is proposed. Moreover, a compression method for the alternative partial bitstreams, which significantly reduces the high storage space requirements of the proposed approach, is presented. Two different hardware decompression schemes have been implemented in a Virtex-5 device and compared in terms of area overhead and decompression latency. Furthermore, a thorough examination has been performed, regarding how the percentage of the spare resources and their allocation in the reconfigurable regions affect the compression efficiency and the processor performance. Finally, the proposed approach has been demonstrated in three different components – ALU, multiplier-accumulator, and instruction-fetch unit – of an open-source embedded processor.     

一种高效的音乐节拍检测算法及其在DSP中的实现

音乐节拍是乐曲中表示固定单位时值和强弱规律的组织形式,亦称拍子。音乐节拍的连续性表现为音乐的平均速度,其单位为bpm（beat per minute）。音乐节拍实时检测并在液晶屏上显示是数字撮盘机必需的功能之一。但是现有的音乐节拍检测算法运算量太大,在数字撮盘机中不可能提供大量的DSP芯片资源来实现作为数字撮盘机附加功能的音乐节拍检测功能。本文从人耳感知音乐节拍的规律和音乐信号的时频特性观察出发,导出了对特定bpm区间的音乐进行准确的bpm检测的最低采样率确定方法,给出了一种极为简单的降采样策略,以及从中提取节拍信息估计出bpm的原理和方法,构成了一种适合数字撮盘机等设备使用的高效的音乐节拍检测算法,并给出了在DSP芯片上的实现步骤和算法测试结果。该算法与现有的音乐节拍检测算法相比,由于既没有聚类检测,也没有高采样率下的多路滤波和频域特征提取等复杂的处理,因此,运算量大大减小,有效地降低了节拍检测对DSP处理速度的要求,使DSP可以更好地实现其它主要的信号处理功能。经验证,节拍检测准确率较高,完全能够满足数字撮盘机中音乐节拍实时检测的需要。      

Processor Speed Control With Thermal Constraints

We consider the problem of adjusting speeds of multiple computer processors, sharing the same thermal environment, such as a chip or multichip package. We assume that the speed of each processor (and associated variables such as power supply voltage) can be controlled, and we model the dissipated power of a processor as a positive and strictly increasing convex function of the speed. We show that the problem of processor speed control subject to thermal constraints for the environment is a convex optimization problem. We present an efficient infeasible-start primal-dual interior-point method for solving the problem. We also present a distributed method, using dual decomposition. Both of these approaches can be interpreted as nonlinear static control laws, which adjust the processor speeds based on the measured temperatures in the system. We give numerical examples to illustrate performance of the algorithms.     

一种基于稀疏矩阵的多核并行扰码方法

针对多核环境中高速无线信号的加扰、解扰,提出了一种基于稀疏矩阵的多核并行扰码方法。首先对输入信号进行串/并转换,并将各路信号分别送入对应的处理器核;考虑基于稀疏矩阵的并行扰码生成器,在单个处理器核内,将其生成的伪随机码与输入信号进行模二加运算,得到单路信号的扰码输出;最后将多路并行的扰码输出变换为串行输出。运算量分析结果表明,采用IEEE 802.11n中的扰码生成多项式,与普通矩阵乘法实现的多核并行扰码方法相比,基于稀疏矩阵的多核并行扰码方法,其运算量降低了一个数量级。     

面向异构信号处理平台的负载均衡算法

针对当前异构信号处理平台中信号处理应用的调度算法优化目标单一且调度结果中处理器负载不均衡的问题，提出了一种基于蚁群优化算法的负载均衡算法。该算法结合蚁群优化算法的快速搜索能力和组合优化能力，以信号处理应用的调度长度和处理器负载均衡为优化目标，对初始信息素矩阵和蚂蚁的遍历顺序进行改进，提出调度长度启发因子和负载均衡启发因子对处理器选择公式进行改进，利用轮盘赌策略确定信号处理应用各子任务分配的处理器，完成信号处理应用的调度。仿真结果表明，该算法得到调度结果在调度长度和负载均衡方面均有改进，可以充分发挥各处理器性能，提高异构信号处理平台的整体效率。