A CMOS mainframe processor with 0.5-μm channel length

A processor chip set with IBM/370 architecture is implemented on five CMOS VLSI chips containing 2.8 million transistors with an effective channel length of 0.5 μm. The chip set consists of the instruction and the fixed-point processor, two cache chips with 16 KB of data and instructions, and the floating-point processor. The chips are implemented in a 1.0-μm technology with three layers of metal. An automatic design system based on the sea-of-gates technique and the standard cell approach was used. The worst-case operating frequency of the chip set is 35 MHz (typically 50 MHz). Four chips of the processor are packaged on a ceramic multichip module. Level-sensitive scan design, built-in self-test, and parity check guarantee high test coverage and reliability     

Design optimization methodology for deep-submicrometer CMOS deviceat low-temperature operation

The design optimization for 0.3-μm channel CMOS technology at liquid-nitrogen temperature (77 K) is described. The tradeoff between circuit performance and reliability for deep-submicrometer CMOS devices at low-temperature operation is theoretically and experimentally examined. A simulator, which selects power-supply voltage and process/device parameters for low-temperature operation, has been developed. Based upon the simulated results, design optimization for low-temperature operation has been proposed to determine power-supply voltage and various process and device parameters. The optimized design has been demonstrated on a 0.3-μm CMOS device, by utilizing electron beam (EB) lithography· Excellent device characteristics and a functional ring oscillator circuit have been obtained at 77 K     

Technology for liquid-nitrogen-cooled computers

Computers requiring 1 to 400 W of refrigeration at 78 K can use standard commercial Gifford-McMahon-type refrigerators similar to those being produced for cryopumps. The computer elements would be immersed in a liquid-nitrogen bath in which heat transfer between the circuit elements and the bath can carry away 5 W/cm². The elements would operate very near the 78-K bath temperature. Vapors from the boiling liquid would be recondensed on the cold refrigerator, located above the bath, and would fall back into the bath. For smaller computers, simple Joule-Thomson refrigerators could be developed. For larger refrigerators, reverse Brayton cycle refrigerators could be developed.     

The execution unit for the VLSI 432 general data processor

The microinstruction execution unit (MEU), which is one of two chips that implement a 32-bit VLSI object-oriented general data processor, is described. A functional overview of the MEU is given and important design tradeoffs are described, including some of the motivations for the particular partitioning of the functions between the two chips. Finally details of circuit implementation are described for some of the more interesting and important circuits on the chip.     

A Low-Temperature Microwave Noise Standard

An X-band thermal noise source is described that consists of a waveguide termination, cooled in a cryogenic environment, along with temperature and pressure monitors and controls. With liquid helium as the cryogen, the effective noise output at the room temperature flange can be set to values around the boiling point of helium (4.2/spl deg/K) with an accuracy of /spl plus mn/ O.O5/spl deg/K. With liquid nitrogen as the cryogen, the output temperature can be set to values around 77/spl deg/K with an accuracy of /spl plus mn/ 0.13/spl deg/K. This accuracy is made possible by several unique features. First, the terminating waveguide section is a vapor bulb thermometer with the absorbing load surrounded with the cryogenic liquid. Second, heat exchangers are used to permit an unusually short waveguide transition seetion between cryogenic and room temperature. Third, an absolute pressure regulator is used to control the cryogen boil-off rate resulting in a temperature stability of 0.003/spl deg/K for helium and 0.02/spl deg/K for nitrogen. At present, the useful accuracy of the standard is limited to /spl plus mn/0.1/spl deg/K because of uncertainties in the insertion loss (about 0.001 dB) of mating room temperature flanges.     

TFT液晶电视控制电路的设计

根据TFT LCD的显示特性，利用KS0127视频译码器和AL251视频扫描同步倍频器及单片机，设计了转换和控制电路，用LCD取代传统的CTR，实现数字色调驱动系统和电视的显示功能，并设计出26.4cm（10.4in）VGA TFT液晶电视的控制卡，叙述了硬件电路设计和软件控制方法以及利用单片机实现I^2C总线控制的实现方法。     

A MIMD-based video signal processing architecture suitable forlarge area integration and a 16.6-cm2 monolithicimplementation

The architecture and implementation of a programmable video signal processor dedicated as building block of a multiple instruction multiple data (MIMD)-based bus-connected multiprocessor system is presented. This system can either be constructed from several single processor chips, or it can be integrated on a large area integrated circuit containing several processors. The processor allows an efficient implementation of different video coding standards like H.261, H.263, MPEG-1 and MPEG-2. It consists of a RISC processor supplemented by a coprocessor for computation intensive convolution-like tasks, which provides a peak performance of more than 1 giga-arithmetic operations per second (GOPS). A large area integrated circuit integrating 9 processor elements (PE's) on an area of 16.6 cm² has been designed. Due to yield considerations redundancy concepts have been implemented, that-even in the presence of production defects-result in working chips utilizing a lower number of PE's. Each PE has built-in self-test (BIST) capabilities, which allow for an independent test of itself under the control of its integrated fault-tolerant BIST controller. Defective PE's are switched off. Only the PE's passing the BIST are used for video processing tasks. Prototypes have been fabricated in a 0.8 μm complementary metal-oxide-semiconductor (CMOS) process structured by masks using wafer stepping with overlapping exposures. Employing redundancy, up to 6 PE's per chip were functional at 66 MHz, thus providing a peak arithmetic performance of up to 6 GOPS     

一种通用低成本大功率高亮度LED封装技术

提出了一种热传导高、热膨胀匹配良好、低成本、大功率、高亮度LED封装技术。该技术采用光电子与微电子技术相结合，利用背面出光的LED芯片，倒装焊接在有双向浪涌和静电保护电路的硅基板上。由于在封装中引入了热膨胀过渡层，在保证良好热膨胀匹配的同时，热阻增加少。采用该封装技术封装的白光LED，发光稳定，光衰小，长期寿命高。     

基于DSP+FPGA视频信号处理器的USB扩展及应用

首先介绍了USB系统结构,并重点阐述了USB接口电路、固件、驱动以及应用程序设计方法.同时,对基于EZ - USBFX2LP系列芯片开发符合USB 2.0系统所涉及到的不同设计方法进行了综合说明与分析.通过实际的数据测试验证,可以满足对视频信号处理设备进行调试的要求.     

On the profile design and optimization of epitaxial Si- andSiGe-base bipolar technology for 77 K applications. II. Circuitperformance issues

For pt.I see ibid., vol.40, no.3, p.525-41 (1993). The circuit performance issues associated with optimizing epitaxial Si- and SiGe-base bipolar technology for the liquid-nitrogen temperature environment are examined in detail. It is conclusively demonstrated that the notion that silicon-based bipolar circuits perform poorly at low temperatures is untrue. Transistor frequency response is examined both theoretically and experimentally, with particular attention given to the differences between SiGe and Si devices as a function of temperature. ECL and NTL ring oscillator circuits were fabricated for each of the four profiles described in pt.I. The minimum ECL gate delay for a SiGe base is essentially unchanged from its room-temperature value. ASTAP models were used to explore circuit operation under typical wire loading. The results indicate that epitaxial-base bipolar technology offers significant leverage for future cryogenic applications     

Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance

Potential challenges with managing mechanical stress distributions and the consequent effects on device performance for advanced 3D integrated circuit (IC) technologies are outlined. A set of physics-based compact models for a multi-scale simulation, to assess the mechanical stress across the device layers in silicon chips stacked and packaged with the 3D through-silicon-via (TSV) technology, is proposed. A calibration technique based on fitting to measured stress components and electrical characteristics of the test-chip devices is presented. For model validation, high-resolution strain measurements in Si channels of the test-chip devices are needed. At the nanoscale, the transmission electron microscopy (TEM) is the only technique available for sub-10 nm strain measurements so far.     

一种新颖的单片集成红外传感信号处理器

介绍一种新颖的单片集成红外传感信号处理器。这种处理器能与多种红外传感器匹配 ,对接收到的传感信号进行处理 ,产生控制信号 ,快速启动各类装置 ,实现自动控制。芯片设计中采用多种抗噪声和低功耗设计技术。本处理器用 1 .2μm双层多晶双层金属 N阱 CMOS工艺实现 ,芯片总面积 2 .7mm2 ,电源电压 5 V时的静态电流为 1 .2 m A,封装后样品测试结果获得设计预期的功能和性能     

Development of a novel stack package to fabricate high density memory modules for high-end application

A new thinking has been spreading rapidly throughout the microelectronics community in the development and application of 3D stack package. Based on the concept, the application of the 3D stack package to high density memory modules makes DRAM provides major opportunities in both miniaturization and integration for advanced and portable electronic products. In order to meet the increasing demands for smaller, higher functionality-integrated and low cost package, this paper presents a packaging method for multi-chip IC without the problem of warpage and pin leakages. Multiple chips are packaged into a single package by stacking up the chips vertically, in which the packaging method is based on the standard wire bond technology with the use of longer bonding wire, appropriate epoxy for delamination and special care in wafer thinning. The presented method promotes the yield of the packaged IC and also successfully reduces the package size. However, special circuit techniques are required to maintain the normal operation of the packaged IC, as well as to maintain the compatible operating speed and power consumption. The reliability of the IC packaged with the presented method has been examined and it verifies the high performance of the presented method.     

Ultrahigh-speed HEMT LSI technology for supercomputer

The current status of high electron mobility transistor (HEMT) technology at Fujitsu for high-performance VLSI is presented, focusing on device performance in the submicrometer dimensional range and the HEMT LSIs implemented in supercomputer systems. The HEMT is a very promising device for ultrahigh-speed LSI/VLSI applications because of the high-mobility GaAs/AlGaAs heterojunction structure. A 1.1 K-gate bus-driver logic LSI has been developed to demonstrate the high-speed data transfer in a high-speed parallel processing system at room temperature, operating at 10.92 GFLOPS. A cryogenic 3.3 K-gate random number generator logic LSI with maximum clock frequency of 1.6 GHz has also been developed to demonstrate the high-clock-rate system operations at liquid-nitrogen temperature. For VLSI level complexity, a HEMT 64-kb static RAM with 1.2-ns access operation and a 45 K-gate gate array with 35-ps logic delay have been developed operating at room temperature, demonstrating the high performance required for future high-speed computer systems     

A 32-Bit Custom VLSI Processor for Communications Network Nodes

Aimed at the application to processors used in communications networks, three kinds of custom CMOS VLSI chips, each integrating approximately 10 kilogates, were developed. During the development of these chips, we overcame various restrictions on the VLSI design, such as input/output pin limitations, bug correction difficulty, and input/output signal delay. A combination of the software and hardware simulators efficiently eliminated logic errors. Microprogram control memory is placed externally to VLSI chips to facilitate tentative correction of possible remaining errors. Two types of processors sharing uniform architecture were also developed for an overall optimum cost-effectiveness using these VLSI chips. One uses all three kinds of VLSI chips and is suitable for switching and communications processing applications. The other includes one VLSI chip and consists of a single printed circuit board. It is suitable for a portable console processor or a processor imbedded in various equipment. These VLSI processors are being introduced in large numbers in communications networks in Japan.     

数字化雷达通用信号处理机设计

本文以4片ADI公司高性能浮点DSP芯片TS201S为核心处理器,结合Xilinx公司高端V5系列FPGA芯片,设计了一种数字化雷达通用信号处理机.处理机通过合理设计总线互联结构、采用高速的串行接口和利用高速电路仿真技术,具有处理能力和数据交互能力强,通用性、可重构性和扩展性好的特点.通过在处理机上实现ISAR实时成像和数字波束形成,验证了处理机的性能和工程实用性.     

The 68040 32-b monolithic processor

A 32-b single-chip processor has been developed that is user object-code compatible with members of the 68000 processor family. The 14-4-mm×15.5-mm device contains over 1.2 million transistors and is fabricated with a double-layer-metal CMOS process. The processor integrates three major functional units: an integer processor: a floating-point processor; and a Harvard-style memory unit. Each major unit is described, and the implementation techniques that were employed and selected circuit issues that were confronted in the design are discussed     

A single chip radix-2 FFT butterfly architecture using parallel data distributed arithmetic

It is shown how distributed arithmetic techniques can be applied in parallel-data arithmetic computations to achieve highly regular and efficient VLSI structures on silicon. Two individual arithmetic processor chips are described as examples of the technique. The chips described, which are intended primarily for computation of the FFT butterfly, each contain the functional equivalence of two parallel pipelined multipliers. The first chip is an 8-bit prototype device which has been designed and fabricated on a standard 5-/spl mu/m silicon-gate n-channel MOS process. The second chip is a 16-bit CMOS-SOS design which uses a modified architecture to achieve higher clocking rates and improved versatility in systems use.     

LHC interaction region quadrupole cryostat production, alignment, and performance summary

The cryostat of a large hadron collider (LHC) interaction region (IR) quadrupole magnet consists of all components of the inner triplet except the magnet assembly itself. It serves to support the magnet accurately and reliably within the vacuum vessel, to provide all required cryogenic piping, and to insulate the cold mass from heat radiated and conducted from the environment. The major components of the cryostat are the vacuum vessel, thermal shield, multi-layer insulation system, cryogenic piping, interconnections, and suspension system. While responsibility for the design and manufacture of the main quadrupole elements is divided between Fermilab and KEK, Fermilab alone is responsible for the design and final assembly of the cryostat for the LHC inner triplets. This paper describes the experience gained during fabrication of the first complete Q2 magnets, the alignment operation and results, and the cryogenic performance of the magnet on the test stand at Fermilab.     

基于TS201平台的雷达信号处理机设计

以ADI公司高性能浮点DSP芯片TS201为核心处理器,结合Xilinx公司VIRTEX-IIPRO系列FPGA芯片设计的2片DSP数据缓存板和4片DSP主处理板,设计了一种雷达信号处理机。该信号处理机中,DSP芯片仅用链路口完成相互间点对点的通信,各自的数据总线互补相连,存储器空间地址彼此独立。系统具有硬件结构体积小,程序易调试,整体可靠性高的优点。