Yttrium- and Terbium-Based Interlayer on SiO2 and HfO2 Gate Dielectrics for Work Function Modulation of Nickel Fully Silicided Gate in nMOSFET

Novel yttrium- and terbium-based interlayers (Y_IL and Tb_IL, respectively) on SiO₂ and HfO₂ gate dielectrics were employed for NMOS work function Phi_m modulation of undoped nickel fully silicided (Ni-FUSI) gate. Bandedge Ni-FUSI gate Phi_m of ~4.11 and ~4.07 eV was obtained by insertion of ultrathin (~1 nm) Y_IL and Tb_IL, respectively, on the SiO₂ gate dielectric in a gate-first process (with 1000 degC anneal). NiSi Phi_m on SiO₂ could also be tuned between the Si midgap and the conduction bandedge E_C by varying the interlayer thickness. The achievement of NiSi Phi_m around 4.28 eV on the HfO₂ gate dielectric using interlayer insertion makes this an attractive Phi_m modulation technique for Ni-FUSI gates on SiO₂ and high-k dielectrics     

Characterization of the Ultrathin HfO2 and Hf-Silicate Films Grown by Atomic Layer Deposition

The physical properties of HfO₂ and Hf-silicate layers grown by the atomic layer chemical vapor deposition are characterized as a function of the Hf concentration and the annealing temperature. The peaks of Fourier transform infrared spectra at 960, 900, and 820 cm_-1 originate from Hf-O-Si chemical bonds, revealing that a Hf-silicate interfacial layer began to form at the HfO₂/SiO ₂ interface after post deposition annealing process at 600 degC for 1 min. Moreover, the intensity of the peak at 750 cm^-1 can indicate the degree of crystallization of HfO₂. The formed Hf-silicate layer between HfO² and SiO² is also confirmed by X-ray photoelectron spectroscopy     

Electrical and Interfacial Characterization of Atomic Layer Deposited High- κ Gate Dielectrics on GaAs for Advanced CMOS Devices

In this paper, electrical and interfacial properties of MOS capacitors with atomic layer deposited (ALD) Al₂O₃, HfO₂, and HfAlO gate dielectrics on sulfur-passivated (S-passivated) GaAs substrates were investigated. HfAlO on p-type GaAs has shown superior electrical properties over Al₂O₃ or HfO₂ on GaAs, and it is attributed to the reduction of the Ga-O formation at the interfacial layer. HfAlO on p-type GaAs exhibits the best electrical properties after postdeposition annealing (PDA) at 500degC. It is found that PDA, at above 500degC, causes a significant amount of Ga and As out-diffusion into the high-k dielectric, which degrades the interface, as well as bulk high-k properties.     

Characteristics of Self-Aligned Gate-First Ge p- and n-Channel MOSFETs Using CVD HfO2 Gate Dielectric and Si Surface Passivation

The electrical properties of p- and n-MOS devices fabricated on germanium with metal-organic chemical-vapor-deposition HfO₂ as gate dielectric and silicon passivation (SP) as surface treatment are extensively investigated. Surface treatment prior to high-K deposition is critical to achieve small gate leakage currents as well as small equivalent oxide thicknesses. The SP provides improved interface quality compared to the treatment of surface nitridation, particularly for the gate stacks on p-type substrate. Both Ge p- and n-MOSFETs with HfO₂ gate dielectrics are demonstrated with SP. The measured hole mobility is 82% higher than that of the universal SiO₂/Si system at high electric field (~0.6 MV/cm), and about 61% improvement in peak electron mobility of Ge n-channel MOSFET over the CVD HfO₂ /Si system was achieved. Finally, bias temperature-instability (BTI) degradation of Ge MOSFETs is characterized in comparison with the silicon control devices. Less negative BTI degradation is observed in the Ge SP p-MOSFET than the silicon control devices due to the larger valence-band offset, while larger positive BTI degradation in the Ge SP n-MOSFET than the silicon control is characterized probably due to the low-processing temperature during the device fabrication     

High Mobility Strained Ge pMOSFETs With High-κ/Metal Gate

Compressively strained Ge long channel ring-type pMOSFETs with high-kappa Si/SiO₂/HfO₂/TiN gate stacks are fabricated on Si_0.2Ge_0.8 virtual substrates. Effective oxide thickness is approximately 1.4 nm with low gate leakage current. A peak hole mobility of 640 cm²/ Vldrs and up to a four times enhancement over the Si/SiO₂ universal curve are observed. Parasitic conduction within the Si-cap layers degrades the mobility at large vertical fields, although up to a 2.5 times enhancement over universal remains at a field of 0.9 MV/cm.     

Group IVB metal oxides high permittivity gate insulators depositedfrom anhydrous metal nitrates

The electrical performance of column IVB metal oxide thin films deposited from their respective anhydrous metal nitrate precursors show significant differences. Titanium dioxide has a high permittivity, but shows a large positive fixed charge and low inversion layer mobility. The amorphous interfacial layer is compositionally graded and contains a high concentration of Si-Ti bonds. In contrast, ZrO₂ and HfO ₂ form well defined oxynitride interfacial layers and a good interface with silicon with much less fixed charge. The electron inversion layer mobility for an HfO₂/SiO_xN_y /Si stack appears comparable to that of a conventional SiO₂ /Si interface     

Spatial Distributions of Trapping Centers in HfO2/SiO2 Gate Stack

An analysis methodology for charge pumping (CP) measurements was developed and applied to extract spatial distributions of traps in SiO ₂/HfO₂ gate stacks. This analysis indicates that the traps accessible by CP measurements in the frequency range down to a few kilohertz are located primarily within the SiO₂ layer and HfO₂/SiO₂ interface region. The trap density in the SiO₂ layer increases closer to the high-kappa dielectric, while the trap spatial profile as a function of the distance from the high-kappa film was found to be dependent on high-kappa film characteristics. These results point to interactions with the high-kappa dielectric as a cause of trap generation in the interfacial SiO₂ layer     

Electrical Properties of Low-Temperature-Compatible P-Channel Polycrystalline-Silicon TFTs Using High-$kappa$ Gate Dielectrics

In this paper, we describe a systematic study of the electrical properties of low-temperature-compatible p-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs) using HfO₂ and HfSiO_x, high-k gate dielectrics. Because of their larger gate capacitance density, the TFTs containing the high-k gate dielectrics exhibited superior device performance in terms of higher I_on/I_off current ratios, lower subthreshold swings (SSs), and lower threshold voltages (V_th), relative to conventional deposited-SiO₂, albeit with slightly higher OFF-state currents. The TFTs incorporating HfSiO_x, as the gate dielectric had ca. 1.73 times the mobility (mu_FE) relative to that of the deposited-SiO₂ TFTs; in contrast, the HfO₂ TFTs exhibited inferior mobility. We investigated the mechanism for the mobility degradation in these HfO₂ TFTs. The immunity of the HfSiO_x, TFTs was better than that of the HfO₂ TFTs-in terms of their V_th shift, SS degradation, mu_FE degradation, and drive current deterioration-against negative bias temperature instability stressing. Thus, we believe that HfSiO_x, rather than HfO₂, is a potential candidate for use as a gate-dielectric material in future high-performance poly-Si TFTs.     

Metal–Oxide–High-$kappa$ Dielectric–Oxide–Semiconductor (MOHOS) Capacitors and Field-Effect Transistors for Memory Applications

Metal-oxide-high-kappa dielectric-oxide-silicon capacitors and transistors are fabricated using HfO₂ and Dy₂O₃ high-kappa dielectrics as the charge storage layer. The programming speed of Al/SiO₂/Dy₂O₃/ SiO₂/Si transistor is characterized by a DeltaV _th shift of 1.0 V with a programming voltage of 12 V applied for 10 ms. As for retention properties, the Al/SiO₂/Dy₂O₃/ SiO₂/Si transistors can keep a DeltaV _th window of 0.5 V for 2 times10⁸ s. The corresponding numbers for Al/ SiO₂/HfO₂/SiO₂/Si transistors are 100 ms and 2 times10⁴ s, respectively. The better performance of the Al/SiO₂/Dy₂O₃/ SiO₂/Si transistors is attributed to the larger conduction band offset at the Dy₂O₃/SiO₂ interface.     

不同退火氛围对TiN/HfO2/SiO2/Si结构电荷分布的影响

热退火技术是集成电路制造过程中用来改善材料性能的重要手段。系统分析了两种不同的退火条件(氨气氛围和氧气氛围)对TiN/HfO₂/SiO₂/Si结构中电荷分布的影响,给出了不同退火条件下SiO₂/Si和HfO₂/SiO₂界面的界面电荷密度、HfO₂的体电荷密度以及HfO₂/SiO₂界面的界面偶极子的数值。研究结果表明,在氨气和氧气氛围中退火会使HfO₂/SiO₂界面的界面电荷密度减小、界面偶极子增加,而SiO₂/Si界面的界面电荷密度几乎不受退火影响。最后研究了不同退火氛围对电容平带电压的影响,发现两种不同的退火条件都会导致TiN/HfO₂/SiO₂/Si电容结构平带电压的正向漂移,基于退火对其电荷分布的影响研究,此正向漂移主要来源于退火导致的HfO₂/SiO₂界面的界面偶极子的增加。     

Carrier Transportation Mechanism of the $hbox{TaN}/ hbox{HfO}_{2}/hbox{IL}/hbox{Si}$ Structure With Silicon Surface Fluorine Implantation

In this paper, the current transportation mechanism of HfO₂ gate dielectrics with a TaN metal gate and silicon surface fluorine implantation is investigated. Based on the experimental results of the temperature dependence of gate leakage current and Fowler-Nordheim tunneling characteristics at 77 K, we have extracted the current transport mechanisms and energy band diagrams for TaN/HfO₂/IL/Si structures with fluorine incorporation, respectively. In particular, we have obtained the following physical quantities: 1) fluorinated and as-deposited interfacial layer (IL)/Si barrier heights (or conduction band offsets) at 3.2 and 2.7 eV; 2) TaN/fluorinated and as-deposited HfO₂ barrier heights at 2.6 and 1.9 eV; and 3) effective trapping levels at 1.25 eV (under both gate and substrate injections) below the HfOF conduction band and at 1.04 eV (under gate injection) and 1.11 eV (under substrate injection) below the HfO₂ conduction band, which contributes to Frenkel-Poole conduction.     

In Situ Comparison of Si/High- $kappa$ and $hbox{Si}/ hbox{SiO}_{2}$ Channel Properties in SOI MOSFETs

Detailed measurements of front- and back-channel characteristics in advanced SOI MOSFETs (ultrathin Si film, high-kappa, metal gate, and selective epitaxy of source/drain) are used to reveal and compare the transport properties at the corresponding Si/high- kappa (HfO₂ or HfSiON) and Si/SiO₂ interfaces. Low-temperature operation magnifies the difference between these two interfaces in terms of carrier mobility, threshold voltage, and subthreshold swing. As compared with Si/SiO₂, the low-field mobility is lower at the Si/high-kappa interface and increases less rapidly at low temperature, reflecting additional scattering mechanisms governed by high-kappa and neutral defects.     

Effects of growth temperature on TDDB characteristics of N2O-grown oxides

Effects of oxide growth temperature on time-dependent dielectric breakdown (TDDB) characteristics of thin (115 Å) N₂O-grown oxides are investigated and compared with those for conventional O₂-grown SiO₂ films with identical thickness. Results show that TDDB characteristics of N₂O oxides are strongly dependent on the growth temperature and, unlike conventional SiO₂, TDDB properties are much degraded for N ₂O oxides with an increase in growth temperature. Large undulations at the Si/SiO₂ interface, caused by locally retarded oxide growth due to interfacial nitrogen, are suggested as a likely cause of degradation of TDDB characteristics in N₂O oxides grown at higher temperatures     

A high performance MIM capacitor using HfO2 dielectrics

Metal-insulator-metal (MIM) capacitors with a 56 nm thick HfO₂ high-κ dielectric film have been fabricated and demonstrated for the first of time with a low thermal budget (~200°C). Voltage linearity, temperature coefficients of capacitance, and electrical properties are all characterized. The results show that the HfO₂ MIM capacitor can provide a higher capacitance density than Si₃N₄ MIM capacitor while still maintaining comparable voltage and temperature coefficients of capacitance. In addition, a low leakage current of 2×10^-9 A/cm² at 3 V is achieved. All of these make the HfO ₂ MIM capacitor to be very suitable for use in silicon RF and mixed signal IC applications     

Constant-Voltage-Bias Stress Testing of a-IGZO Thin-Film Transistors

Constant-voltage-bias (V_DS = V_GS = 30 V) stress measurements are performed for a period of 10⁵ s on thin-film transistors (TFTs) with amorphous indium-gallium-zinc-oxide (IGZO) channel layers fabricated via RF sputtering using a postdeposition annealing temperature of 200degC, 250degC, or 300degC. Thermal silicon dioxide is employed as a TFT bottom-gate insulator. All SiO₂/IGZO TFTs tested exhibit the following: 1) a positive rigid log(I_D)- V_GS transfer curve shift; 2) a continuous drain-current decrease over the entire stress duration; and 3) recovery of the log(I_D)-V_GS transfer curve toward the prestressed state when the stressed TFT is left unbiased in the dark at room temperature for an extended period of time. The SiO₂/IGZO TFTs subjected to a higher postdeposition annealing temperature are more stable. A small (and typically negligible) amount of clockwise hysteresis is present in the log(I_D) -V_GS transfer curves of IGZO TFTs. These instability and hysteresis observations are consistent with a SiO₂/ IGZO TFT instability mechanism involving electron trapping within the IGZO channel layer.     

Influence of Hydrogen Incorporation on the Reliability of Gate Oxide Formed by Using Low-Temperature Plasma Selective Oxidation Applicable to Sub-50-nm W-Polymetal Gate Devices

This letter reveals the physical and electrical properties of silicon dioxide (Si02) formed by the plasma selective oxidation (plasma selox) using 02 and H2 gas mixture, which is applicable to sub-50-nm tungsten-polymetal gate memory devices without capping nitride film. Metal-oxide-semiconductor capacitors with gate oxide formed by the plasma selox at the process temperature in the range of 400degC-700degC showed much better time-dependent dielectric-breakdown characteristics than those formed by the conventional thermal selox at 850degC. On the other hand, in the case of very low temperature (25degC) plasma selox, the gate oxide degradation such as initial breakdown was found. It turned out to be due to the excessive hydrogen and water incorporation into the SiO₂ layer through thermal desorption spectroscopy measurements.     

Full-Band Tunneling in High-κ Oxide MOS Structures

In this paper, we investigate the tunneling properties of ZrO₂ and HfO₂ high-k oxides, by applying quantum mechanical methods that include the full-band structure of Si and oxide materials. Semiempirical sp³s*d tight-binding parameters have been determined to reproduce ab-initio band dispersions. Transmission coefficients and tunneling currents have been calculated for Si/ZrO₂/Si and Si/HfO₂/Si MOS structures, showing a very low gate leakage current in comparison to SiO₂-based structures with the same equivalent oxide thickness. The complex band structures of ZrO₂ and HfO₂ have been calculated and used to develop an energy-dependent effective tunneling mass model. We show that effective mass calculations based on this model yield tunneling currents in close agreement with full-band results.     

A Comparative Study of HfTaON/SiO2 and HfON/SiO2 Gate Stacks With TaN Metal Gate for Advanced CMOS Applications

The electrical characteristics of a novel HfTaON/SiO₂ gate stack, which consists of a HfTaON film with a dielectric constant of 23 and a 10-Aring SiO₂ interfacial layer, have been investigated for advanced CMOS applications. The HfTaON/SiO₂ gate stack provided much lower gate leakage current against SiO₂ , good interface properties, excellent transistor characteristics, and superior carrier mobility. Compared to HfON/SiO₂, improved thermal stability was also observed in the HfTaON/SiO₂ gate stack. Moreover, charge-trapping-induced threshold voltage V _th instability was examined for the HfTaON/SiO₂ and HfON/SiO₂ gate stacks. The HfTaON/SiO₂ gate stack exhibited significant suppression of the V_th instability compared to the HfON/SiO₂, in particular, for nMOSFETs. The excellent performances observed in the HfTaON/SiO₂ gate stack indicate that it has the potential to replace conventional SiO₂ or SiON as gate dielectric for advanced CMOS applications     

Work Function Tunability of Refractory Metal Nitrides by Lanthanum or Aluminum Doping for Advanced CMOS Devices

A lanthanum (La)-doped HfN is investigated as an n-type metal gate electrode on SiO₂ with tunable work function. The variation of La concentration in (HfinfinLa_1-x)N_y modulates the gate work function from 4.6 to 3.9 eV and remains stable after high-temperature annealing (900degC to 1000degC), which makes it suitable for n-channel MOSFET application. An ultrathin high-fc dielectric layer was formed at the metal/SiO₂ interface due to the (HfinfinLa_1-x)N_y and SiO₂ interaction during annealing. This causes a slight reduction in the effective oxide thickness and improves the tunneling current of the gate dielectric by two to three orders. We also report the tunability of TaN with Al doping, which is suitable for a p-type metal gate work function. Based on our results, several dual-gate integration processes by incorporating lanthanum or aluminum into a refractory metal nitride for CMOS technology are proposed.     

Electrical properties of MOSFET's with N2O-nitridedLPCVD SiO2 gate dielectrics

Electrical properties of MOSFETs with gate dielectrics of low-pressure chemical-vapor-deposited (LPCVD) SiO₂ nitrided in N₂O ambient are compared to those with control thermal gate oxide. N₂O nitridation of CVD oxide, combines the advantages of interfacial oxynitride growth and the defectless nature of CVD oxide. As a result, devices with N₂O-nitrided CVD oxide show considerably enhanced performance (higher effective electron mobility), improved reliability (reduced charge trapping, interface state generation, and transconductance degradation), and better time-dependent dielectric breakdown (TDDB) properties (t_BD ) compared to devices with control thermal oxide