基于变周期重播种LFSR的测试生成

基于重播种的LFSR结构的伪随机测试生成中包含的冗余测试序列较多,因而其测试序列长度仍较长,耗费测试时间长,测试效率不高。针对此状况,提出基于变周期重播种的LFSR结构的测试生成方法。该方法可以有效地跳过伪随机测试生成中的大量冗余测试序列。在保证电路测试故障覆盖率不变的条件下,缩短总测试序列的长度。分析结果表明,同定长重播种方法相比,该方法能以较少的硬件开销实现测试序列的精简,加快了测试的速度,提高了电路测试诊断的效率。     

重新播种的测试方法研究

重新播种的测试方法是一种内建自测试方法,它可以用来提高伪随机测试矢量的故障覆盖率。介绍了 三种重新播种的测试方法,它们分别是使用很少种子的内建自测试重新播种方法、多重多项式线性反馈移位寄存器 的重新播种方法和使用部分线性反馈移位寄存器的重新播种方法。这三种方法在测试的硬件开销方面或在编码效率 等方面有所改进。     

A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters

In this paper a new scheme for deterministic and mixed mode scan-based BIST is presented. It relies on a new type of test pattern generator which resembles a programmable Johnson counter and is called folding counter. Both the theoretical background and practical algorithms are presented to characterize a set of deterministic test cubes by a reasonably small number of seeds for a folding counter. Combined with classical approaches for test width compression and with pseudo-random pattern generation these new techniques provide an efficient and flexible solution for scan-based BIST. Experimental results show that the proposed scheme outperforms previously published approaches based on the reseeding of LFSRs or Johnson counters.     

Deterministic built-in test pattern generation for high-performancecircuits using twisted-ring counters

We present a new approach for built-in test pattern generation based on the reseeding of twisted-ring counters (TRCs). The proposed technique embeds a precomputed deterministic test set for the circuit under test (CUT) in a short test sequence produced by a TRC. The TRC is designed using existing circuit flip-flops and does not add to hardware overhead beyond what is required for basic scan design. The test control logic is simple, uniform for all circuits, and can be shared among multiple CUTs. Furthermore, the proposed method requires no mapping logic between the test generator circuit and the CUT; hence it imposes no additional performance penalty. Experimental results for the ISCAS benchmark circuits show that it is indeed possible to embed the entire precomputed test set in a TRC sequence using only a small number of seeds     

Test-decompression mechanism using a variable-length multiple-polynomial LFSR

A new test-decompression methodology using a variable-rank multiple-polynomial linear feedback shift register (MP-LFSR) is proposed. In the proposed reseeding scheme, a test cube with a large number of specified bits is encoded with a high-rank polynomial, while a test cube with a small number of specified bits is encoded with a low-rank polynomial. Therefore, according to the number of specified bits in each test cube, the size of the encoded data can be optimally reduced. A variable-rank MP-LFSR can be implemented with a slight modification of a conventional MP-LFSR. The experimental results on the largest ISCAS'89 benchmark circuits show that the proposed methodology can provide much better encoding efficiency than the previous methods with adequate hardware overhead.     

基于动态覆盖率提高门槛值的种子计算方法

为了向可重复播种的LFSR结构提供种子,提出一种基于动态覆盖率提高门槛值(Dynamic Coverage Im-provement Threshold,DCIT)的种子计算方法.使用该方法计算得到的种子进行重复播种,能够截断对提高故障覆盖率效率低的测试码序列.每个种子可以得到长度固定的伪随机测试序列.以ISCAS85基准电路实验结果表明,该方案能够在不降低故障覆盖率的前提下,减少测试矢量长度、缩短测试时间和降低测试功耗.     

Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns

This paper presents a new reseeding technique that reduces the storage required for the seeds as well as the test application time by alternating between ATPG and reseeding to optimize the seed selection. The technique avoids loading a new seed into the PRPG whenever the PRPG can be placed in a state that generates test patterns without explicitly loading a seed. The ATPG process is tuned to target only undetected faults as the PRPG goes through its natural sequence which is maximally used to generate useful test patterns. The test application procedure is slightly modified to enable higher flexibility and more reduction in tester storage and test time. The results of applying the technique show up to 90% reduction in tester storage and 80% reduction in test time compared to classic reseeding. They also show 70% improvement in defect coverage when the technique is emulated on test chips with real defects.     

An Optimized Seed-based Pseudo-random Test Pattern Generator: Theory and Implementation

This paper presents a novel seed-based test pattern generator (SB-TPG). The core of SB-TPG is a seed sequence generator. A coverage-driven seed generation algorithm has been proposed to generate the optimized seeds. The test sequence generated by SB-TPG is a single input change (SIC) sequence that can significantly reduce test power for test-per-clock built-in self-test (BIST). Further, seed-masking technique has been put forward to filter those power-consuming seeds, thus reducing test power for test-per-scan BIST. Experimental results show that SB-TPG can achieve high fault coverage with short test length, low power and small hardware overhead.     

Optimization of test parallelism with limited hardware overhead

The main considerations for built-in self-test (BIST) for complex circuits are fault coverage, test time, and hardware overhead. In the BIST technique, exhaustive or pseudo-exhaustive testing is used to test the combinational logic in a register sandwich. If register sandwiches can be identified in a complex digitial system, it is possible to test several of them in parallel using the built-in logic block observation (BILBO) technique. Concurrent built-in logic block observation (CBILBO) technique can further improve the test time, but it requires significant hardware overhead. A systematic scheduling technique is suggested to optimize parallel tests of register sandwiches. Techniques are proposed to deal with shared registers for parallel testing. The proposed method attempts to reduce further the test time while only modestly increasing the hardware overhead.     

Low Power BIST by Filtering Non-Detecting Vectors

In this paper, two techniques to reduce the energy and the average power consumption of the system are proposed. They are based on the fact that as the test progresses, the detection efficiency of the pseudo-random vectors decreases very quickly. Many of the pseudo-random vectors will not detect faults in spite of consuming a significant amount of energy from the power supply. In order to prevent this energy consumption, a filtering of the non-detecting vectors and a reseeding strategy are proposed.These techniques are evaluated on the set of ISCAS-85 benchmark circuits. Extensive simulations have been made using the SAIL energy simulator showing that, in large circuits, the energy consumption and the average power savings reach 90.0% with a mean value of 74.2% with the filtering technique, and 97.2% with an average value of 90.9% with the reseeding strategy.     

C-testable design techniques for iterative logic arrays

A design-for-testability (DFT) approach for VLSI iterative logic arrays (ILA's) is proposed, which results in a small constant number of test patterns. Our technique applies to arrays with an arbitrary dimension, and to arrays with various connection types, e.g., hexagonal or octagonal ones. Bilateral ILA's are also discussed. The DFT technique makes general ILA's C-testable by using a truth-table augmentation approach. We propose an output-assignment algorithm for minimizing the hardware overhead. We give a CMOS systolic array multiplier as an example, and show that an overhead of no more than 5.88% is sufficient to make it C-testable, i.e., 100% single cell-fault testable with only 18 test patterns regardless of the word length of the multiplier. Our technique guarantees that the test set is easy to generate. Its corresponding built-in-self-test structures are also very simple     

An Accurate and Cost-Effective Jitter Measurement Technique Using a Single Test Frequency

An accurate and cost-effective jitter measurement technique is proposed. The new technique uses only a single test with a high frequency input sine wave. Eliminating the need for a 2nd low frequency test, which is required in the conventional dual-frequency jitter test, provides significantly savings in both hardware and data acquisition time. The new technique is computationally efficient since it requires only one FFT together with some simple time domain computation. Furthermore, there are no nonlinear operations involved, hence avoiding errors inherently associated with such operations. Theoretical analysis, extensive simulation results and experimental results show that the proposed technique is cost-effective and achieves comparable test accuracy to that achieved by the conventional dual-frequency test. The new technique is reliable and robust to both harmonic and non-harmonic distortions. The algorithmic simplicity and the relaxed hardware requirement make the new technique potentially suited for built-in self test.     

A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment

A new scan architecture for both low power testing and test volume compression is proposed. For low power test requirements, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the distribution of unspecified bits in the test cubes. In order to optimize the proposed process, a novel graph-based heuristic is proposed to partition the scan chains into several segments. For test volume reduction, a new LFSR reseeding based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, s _max, virtually. The performance of a conventional LFSR reseeding scheme highly depends on s _max. In this paper, by using different clock phases between an LFSR and scan chains, and grouping the scan cells by a graph-based grouping heuristic, s _max could be virtually reduced. In addition, the reduced scan rippling in the proposed test compression scheme can contribute to reduce the test power consumption, while the reuse of some test results as the subsequent test stimulus in the low power testing scheme can reduce the test volume size. Experimental results on the largest ISCAS89 benchmark circuits show that the proposed technique can significantly reduce both the average switching activity and the peak switching activity, and can aggressively reduce the volume of the test data, with little area overhead, compared to the previous methods.

Modified Overlap Technique Using Fermat and Mersenne Transforms

This brief presents a simple and efficient technique for extending the usefulness of Fermat and Mersenne transforms. The constraint on transform length and wordlength is reduced by employing the proposed modified overlap technique, yielding practical architectures for convolution. The proposed technique relies on using transforms of different lengths operating in parallel with output samples time aligned. The brief presents an analysis of the hardware costs of the proposed scheme.     

A HW/SW Co-Verification Technique for FPGA Test

Field programmable gate arrays （FPGAs） have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/software （HW/SW） co-verification technique for FPGA test is proposed in this paper. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, this technique is capable of testing each input/output block （IOB） and configurable logic block （CLB） of FPGA automatically, exhaustively and repeatedly. Fault cells of FPGA can be positioned automatically by the proposed approach. As a result, test efficiency and reliability can be enhanced without manual work.     

基于跨度和虚拟层的三维芯核测试外壳扫描链优化方法

为减少三维芯核绑定前和绑定后的测试时间,降低测试成本,提出了基于跨度和虚拟层的三维芯核测试外壳扫描链优化方法.所提方法首先通过最大化每条测试外壳扫描链的跨度,使得绑定前高层电路和低层电路的测试外壳扫描链数量尽可能相等.然后,在TSVs(Through Silicon Vias)数量的约束下,逐层的将虚拟层中的扫描元素分配到测试外壳扫描链中,以平衡绑定前后各条测试外壳扫描链的长度.实验结果表明,所提方法有效地减少了三维芯核绑定前后测试的总时间和硬件开销.     

基于探索式分区和测试向量生成的硬件木马检测方法

本文提出基于分区和最优测试向量生成的硬件木马检测方法.首先,采用基于扫描细胞分布的分区算法将电路划分为多个区域.然后,提出测试向量重组算法,对各区域依据其自身结构生成近似最优的测试向量.最后,进行分区激活和功耗分析以检测木马,并采用信号校正技术消减制造变异和噪声的影响.优点是成倍提高了检测精度,克服了制造变异的影响,解决了面对大电路的扩展性问题,并可以定位木马.在基准电路上的验证实验表明检测性能有较大的提升.     

Low-Cost Fast VLSI Algorithm for Discrete Fourier Transform

A primeN-length discrete Fourier transform (DFT) can be reformulated into a (N-1)-length complex cyclic convolution and then implemented by systolic array or distributed arithmetic. In this paper, a recently proposed hardware efficient fast cyclic convolution algorithm is combined with the symmetry properties of DFT to get a new hardware efficient fast algorithm for small-length DFT, and then WFTA is used to control the increase of the hardware cost when the transform length Nis large. Compared with previously proposed low-cost DFT and FFT algorithms with computation complexity of O(logN), the new algorithm can save 30% to 50% multipliers on average and improve the average processing speed by a factor of 2, when DFT length Nvaries from 20 to 2040. Compared with previous prime-length DFT design, the proposed design can save large amount of hardware cost with the same processing speed when the transform length is long. Furthermore, the proposed design has much more choices for different applicable DFT transform lengths and the processing speed can be flexible and balanced with the hardware cost     

Interleaver pruning for construction of variable-length turbo codes

In this paper, we address the issue of pruning (i.e., shortening) a given interleaver in a parallel concatenated convolutional code (PCCC). The principle goal of pruning is that of construction of variable-length and hence delay interleavers with application to PCCC, using the same structure (possibly in hardware) of the interleaver and deinterleaver units. As a side benefit, it is sometimes possible to reduce the interleaver length and hence delay for nearly the same and sometimes even better asymptotic performance. In particular, we present a systematic technique for interleaver pruning and demonstrate the average optimality of the strategy. Sample simulation results are presented confirming the average optimality of the proposed scheme.     

A concurrent built-in self-test architecture based on a self-testing RAM

Manufacturing test is carried-out once to ensure the correct operation of the circuit under test right after fabrication, while testing is carried-out periodically to ensure that the circuit under test continues to operate correctly on the field. The use of offline built-in self-test (BIST) techniques for periodic testing imposes the interruption of the normal operation of the circuit under test. On the other hand, the use of input vector monitoring concurrent BIST techniques for periodic testing provides the capability to perform the test, while the circuit under test continues to operate normally. In this paper, a novel input-vector monitoring concurrent BIST technique for combinational circuits based on a self-testing RAM, termed R-CBIST, is presented. The presented technique compares favorably to the other input vector monitoring concurrent BIST techniques proposed so far with respect to the hardware overhead, and the time required for the concurrent test to be completed (concurrent test latency). R-CBIST can be utilized to test ROM because it results in small hardware overhead, whereas there is no need to stop the ROM normal operation.