精细间距BGA用PCB的设计与制作探讨

主要针对BGA电气连接设计做了简要阐述,并对高密BGA生产过程中存在的潜在可靠性影响做了分析。文章从一款0.4mm间距BGA的PCB板设计入手综合叠层规则、电气连接设计、信号回流、选材、表面处理等几个方面的考虑,在0.4mm间距BGA焊盘上采用盘中通孔和盲埋孔相结合的方式将其开发制作成功。     

提高BGA焊接的可靠性方法与实践

结合工作实际和经验，对BGA焊点失效的样品进行分析和BGA焊点的可靠性等问题进行论述，特别对PCB焊盘的选择、设计以及模板的开孔方式等的改进，提出一些改善BGA焊点质量和可靠性的工艺方法，在实践中取到很好的效果。     

文献与摘要（39）

球栅阵列封装板的连接盘图形 Land Patterns for BGA Packages 球栅阵列(BGA)封装按照I/O端子节距的不同分为粗节距型(节距大于0.8mm)与细节距型(节距0.8mm及以下),不同节距对焊球直径、焊盘直径、阻焊间隙应有不同设计要求。本文列出了推荐的设计尺寸。通常焊盘直径     

一种印制电路板BGA焊盘脱落应急修复方法

介绍了BGA封装的概念及其分类;以实际工程实例为背景,对整个应急修复过程做了全面、细致的阐述,并由此总结出了BGA焊盘脱落的修复工艺流程;从而证明了该修复方法的通用性与实用性,为印制电路板BGA焊盘脱落修复提供了一种有效的应急解决途径.     

BGA焊接与植球工艺探讨

本文主要介绍了印制板焊盘设计对BGA焊接质量的影响，深入探讨了BGA的焊接工艺方法，并结合工作实际进行了BGA器件修复的研究。     

国际电子工业联接协会出版IPC-7095B版标准

IPC-国际电子工业联接协会出版了IPC-7095B版标准,即《BGA的设计及组装工艺的实施》。实施球栅阵列（BGA）和细间距BGA（FBGA）技术对设计、组装、检验和返修人员带来了特有的挑战。IPC-7095B为目前正在使用BGA或者有意转向采用面积阵列封装设计的公司提供了非常实用的信息。目前BGA封装所用合金及将其连接到印制板连接盘上所用的焊料合金正在经历着从有铅转向无铅的巨大变革,     

塑封BGA的焊接与植球

本主要介绍了印制板焊盘设计对BGA焊接质量的影响，深入探讨了塑封BGA的焊接工艺方法，并结合工作实际进行了BGA器件修复的研究。     

堆叠结构BGA焊接可靠性评价方法

设计了基于实时监测菊花链拓扑结构动态电阻的叠层球栅阵列封装(BGA)焊接可靠性评价方法,使用该方法研究叠层器件BGA焊接互连结构的环境可靠性.以基于硅通孔(TSV)技术的BGA互连的硅基双层器件为例,首先通过有限元仿真确定叠层器件各层焊点在-55～125℃条件下的应变和应力,并根据应变和应力将每一叠层焊点划分为敏感焊点和可靠焊点;然后将敏感焊点通过器件键合焊盘、键合丝、TSV、垂直过孔、可靠焊点和PCB布线相连接形成菊花链.由于敏感焊点是菊花链的薄弱环节,可以通过监测菊花链电阻变化来研究叠层器件的环境可靠性,并以此为基础设计了堆叠结构BGA产品焊接可靠性试验系统.该方法简单高效,能快速解决常规失效分析方法无法检测的BGA虚焊接、微小缺陷等问题.     

文献与摘要（76）

球栅阵列/印制电路板的互联设计指南BGA/PCB Interconnect Design Guidelines球栅阵列(BGA)是一种用于集成电路的封装形式。在印制板(PCB)组装过程中,焊球应用于BGA底部引脚,并贴装到同一引脚位置的印制板上。本文描述BGA/PCB设计的细节,包括针对1.27mm、1mm、     

弯曲应力状况下微型BGA封装可靠性比较研究

微型球栅阵列（μBGA）是芯片规模封装（CSP）的一种形式,已发展成为最先进的表面贴装器件之一。在最新的IxBGA类型中使用低共晶锡．铅焊料球,而不是电镀镍金凸点。采用传统的表面贴装技术进行焊接,研讨μBGA的PCB装配及可靠性。弯曲循环试验（1000～1000με）,用不同的热因数（Qη）回流,研究μBGA、PBGA和CBGA封装的焊点疲劳失效问题。确定液相线上时间,测定温度,μBGA封装的疲劳寿命首先增大,接着随加热因数的增加而下降。当Q。接近500S·℃时,出现寿命最大值。最佳Qη范围在300-750s·℃之间,此范围如果装配是在氮气氛中回流,μBGA封装的寿命大于4500个循环。采用扫描电子显微镜（SEM）,来检查μBGA和PBGA封装在所有加热N数状况下焊点的失效。每个断裂接近并平行于PCB焊盘,在μBGA封装中裂纹总是出现在焊接点与PCB焊盘连接的尖角点,接着在Ni3Sn4金属间化合物（IMC）层和焊料之间延伸。CBGA封装可靠性试验中,失效为剥离现象,发生于陶瓷基体和金属化焊盘之间的界面处。     

0.5mm间距BGA芯片的PCB设计

目前,在高速PCB设计中,0.8mm间距BGA芯片的应用已非常普遍,但0.5mm间距BGA芯片的设计和焊接应用则相对较少。文章结合多层线路板的叠层规则、布线设计、信号回流以及钻孔工艺等技术,采用在0.5mm间距BGA芯片的焊盘上直接设计盘中通孔和一阶盲孔。在将PCB成本控制在规定预算范围内的同时,成功的将0.5mm间距BGA芯片应用在高密度互连PCB的研究与开发中。从生产出小批量单板的焊接情况看,系统上电后运行稳定,不存在短路和虚焊情况,从而较好的实现了电路工作性能,达到预先设计目标。     

Board level solder joint reliability analysis and optimization of pyramidal stacked die BGA packages

Due to requirements of cost-saving and miniaturization, stacked die BGA has recently gained popularity in many applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of wirebond stacked die BGA is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux's approach with non-linear viscoplastic analysis of solder joints. The critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house TFBGA (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyses are performed to study the effects of 16 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, smaller top and bottom dice sizes, thicker top or bottom die, thinner PCB, thicker substrate, higher solder ball standoff, larger solder mask opening size, smaller maximum ball diameter, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. The effect of number of layers of stacked-die is also investigated. Finally, design optimization is performed based on selected critical design variables.     

影响BGA封装焊接技术的因素研究

虽然表面贴装制造工艺已经纯熟,但是随着BGA封装的广泛应用以及焊球间距的逐步减小,给表面贴装制造工艺带来了新的挑战.基于BGA封装在表面贴装技术焊接中的应用,从印制电路板焊盘设计、印制电路板板材选取和保护、BGA封装选取和保护、印刷工艺、回焊炉温度曲线设定与控制等方面,阐述了影响BGA封装焊接技术的各个因素,进而提升B...     

A visualization-based approach for bump-pad/IO-ball placement and routing in flip-chip/BGA technology

The routing problem in area array integrated circuit (IC) packaging has become an extremely complex problem in the realm of high I/O count IC packages. With the advent of flip-chip and ball grid array (BGA) technology to meet the current demands of smaller size and high wiring densities, the routing problem lies in the core of electronic design automation process. In this paper, we describe an intuitive computer visualization-based approach for placement and routing of bonding pads that would result in low manufacturing costs and smaller component size compared to conventional approaches. This novel approach is an extension of "balls shifted as needed" method for I/O ball placement in BGA package enabling single-layer board-level routing for any I/O count. The I/O ball/pad layout and routing designs along with results are presented for two routing layers with the inclusion of vias in the design. This routing scheme is shown to be easily extensible to accommodate more practical multilayer routing and can be incorporated in current electronic design automation (EDA) computer-aided design (CAD) tools to offer an integrated routing solution for area array chip-package-board codesign. The results show that different trace routing patterns lead to different area requirements for same number of I/Os. This has led to the formulation of new design paradigms which are presented in the paper for smaller component size.     

Board level solder joint reliability analysis of stacked die mixed flip-chip and wirebond BGA

Stacked die BGA has recently gained popularity in telecommunication applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of lead-free stacked die BGA with mixed flip-chip (FC) and wirebond (WB) interconnect is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. Based on the FC–WB stack die configuration, the critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house lead-free TFBGA46 (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyzes are performed to study the effects of 20 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, thinner PCB and mold compound, thicker substrate, larger top or bottom dice sizes, thicker top die, higher solder ball standoff, larger solder mask opening, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. SnAgCu is a common lead-free solder, and it has much better board level reliability performance than eutectic solder based on modeling results, especially low stress packages.     

BGA密集孔耐热性能影响因素分析

文章以球栅阵列（BGA）密集孔耐热性能影响因素进行分析，考虑多层压合、机械钻孔、湿处理等工艺流程参数对耐热性能的影响，通过DOE方式，确定各制程对耐热性的影响程度，优化加工参数，改善BGA孔耐热性能。     

盘中孔板黑孔及焊点脱落改善探讨

随着线路的精细化发展,PCB布线密度越来越高,部分BGA板已取消通孔与焊球间的引线设计,为此须将BGA焊点与通孔重叠即制作成盘中孔工艺,以满足更高密度的布线需求。传统的盘中孔制作大多采用油墨或树脂塞孔再沉铜电镀的工艺生产,此工艺总是面临塞孔不饱满/黑孔/结合力不足等缺陷,给后续焊接带来极大的品质隐患。本文主要针对盘中孔黑孔及结合力不足进行了验证分析,并通过工艺优化进行了有效改善,大大提高了生产品质及一次性良率。     

New dummy design and stiffener on warpage reduction in Ball Grid Array Printed Circuit Board

Printed Circuit Board (PCB) warpage increases as thickness decreases and ultimately is attributed to CTE mismatch and thickness geometry of the components. Recently, a thin Ball Grid Array (BGA) PCB has been developed due to the advantages like high electrical translation speed with low signal noise. Large warpage severely limited by BGA PCB performance leads to reliability issues modes such as crack and delamination between interconnection components. This is why a dummy design on a BGA PCB and metal stiffener on a Flip Chip (FC) BGA PCB warpage are analyzed experimentally.At the first step, new dummy design in BGA PCB (BoC type) is proposed to reduce warpage. The new dummy design is shaped as a bar. Results of the statistical experimental analysis show PCB warpage using the new dummy design is significantly reduced compared to the use of a PCB with a conventional dummy design. Furthermore, the new dummy design decreases PCB warpage by about 67%. These results signify that the stiffness of the BoC PCB is improved by the new dummy design because the bar-shaped Cu pattern in the dummy acts as a rigid bar stiffener.At the second step, metal stiffener effect is studied to reduce coreless FCBGA PCB warpage. Coreless FCBGA PCB, coreless FCBGA package, and specimens with non-symmetric structure are considered to determine metal stiffener effect on warpage. The experimental results show that metal stiffener has high stiffness, and it seems very effective on reducing average and standard deviation of coreless PCB warpage.     

Effect of thermocapillary action in the underfill encapsulation of multi-stack ball grid array

Recent trend in electronic industries are demanding smaller chip packaging process along with increase in performance and reliability of the package. The introduction of Multi-stack Ball Grid Array (BGA) to enhance the performance of the conventional BGA flip chip has frequently encountered several hitches such as extended filling time and incomplete filling at the upper layer of the multi-stacks BGA. It has been found that the encapsulant lacks energy to flow at the upper layer due to lower hydrostatics pressure. In this paper, a straightforward solution by incorporating additional thermal energy in the encapsulant to increases its flow ability is introduced. This additional thermal energy at the upper layer produces a distinct temperature difference between the upper and lower layers, or simply thermal delta. This research attempts to demonstrate the effectiveness of thermal delta in solving the aforementioned flow problem during encapsulation process of multi-stacks BGA, by means of experiment and numerical simulation. The findings have shown that the experimental data compares well with the simulation results. It was also found that the implementation of thermal delta substantially reduces the filling time across the multi-stack packages. This study reveals the potential of thermocapillary-driven underfill encapsulation being widely adopted in future industrial encapsulation of multi-stacks BGA packaging.     

用氢等离子清洗改善BGA的可焊性

BGA器件的焊球往往都非常容易氧化,焊接后的BGA焊点不仅外观上不过关,其电性能和热性能也大打折扣。但是BGA焊球的去氧化问题一直没有很好的解决方法。介绍一种氢等离子体再流焊去氧化物的方法,该方法把氢等离子体和适度加热有机地结合在一起,能有效地去除BGA焊球表面的氧化物。该方法工艺简单,效果显著,效率也很高,是清除BGA元器件和其他表面贴装元器件氧化物的最佳方法。